In this paper, the newly-found time-dependent layout dependent effects (LDE) due to layout dependency of device aging is presented. BTI and HCI degradation in nanoscale HKMG devices exhibits evident layout dependency,...
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ISBN:
(纸本)9781509003211
In this paper, the newly-found time-dependent layout dependent effects (LDE) due to layout dependency of device aging is presented. BTI and HCI degradation in nanoscale HKMG devices exhibits evident layout dependency, which will significantly complicate the circuit design. With the analysis on circuit level, the time-dependent LDE should be considered to ensure enough design margin, especially at end of life. This work is helpful to design-technology co-optimization at nanoscale nodes.
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E-TSPC) scheme is presented. By restricting the short-circuit current in noncritical branchs, the design reduces the m...
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ISBN:
(纸本)9781479953424
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E-TSPC) scheme is presented. By restricting the short-circuit current in noncritical branchs, the design reduces the major source of power dissipation in E-TSPC scheme. The presented design enhances the maximum working frequency with shorter critical path and lower load capacitances. Simulation results in SMIC 40nm process show that compared with referenced E-TSPC based designs at least 61.2% (divide-by-2) and 41.1% (divide-by-3) reduction in power delay product (PDP) can be achieved by the proposed design.
A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by t...
A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and the excellent ESD performance.
We theoretically investigate the spin injection in different FM/I/n-Si tunnel contacts by using the lattice NEGF method. We find that the tunnel contacts with low barrier materials such as TiO2 and Ta2O5, have much lo...
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The 4H-SiC n-p-n BJT for ultraviolet detection with high optical gain is proposed and optimized in this paper. The effect of structural parameters of 4H-SiC phototransistor on the performance of the detectors is simul...
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The n-p-i-n AlGaN solar-blind ultraviolet double heterojunction phototransistor (DHPT) with internal gain is proposed and optimized in this paper. The dependences of spectral responsivity and quantum gain on structure...
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Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a ...
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Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a wafer-level characterization method is proposed in this work. By separating the detection rail from the supply rail, triggering actions resulted from detection circuits can be clearly captured by the proposed method. Besides, both the component-level triggering criteria and system-level transient-induced latch-up (TLU) immunity of ESD protection circuits can be fully characterized by the proposed method. Silicon-data based case studies are presented in this work to verify the validity of the proposed method.
A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of ...
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ISBN:
(纸本)9781479953424
A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to ×4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5～40 cycles to finish locking.
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