检索结果-内蒙古大学图书馆

Heavy ion induced electrical property degradation in sub-100 nm bulk silicon MOS devices

Journal of Semiconductors 2015年第11期36卷 30-33页

作者：陈叶华安霞武唯康张曜刘静静张兴黄如 Peking University Shenzhen Graduate School Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University School of Software and Microelectronics Peking University

The radiation response of 90 nm bulk silicon MOS devices after heavy ion irradiation is experimentally investigated. Due to the random strike of the incident particle, different degradation behaviors of bulk silicon MOS devices are observed. The drain current and maximum transconductance degrade as a result of the displacement damage in the channel induced by heavy ion strike. The off-state leakage current degradation and threshold voltage shift are also observed after heavy ion irradiation. The results suggest that the radiation induced damage of sub-100 nm MOS devices caused by heavy ion irradiation should be paid attention.

关键词： heavy ion displacement damage bulk silicon

来源：评论

学校读者我要写书评

暂无评论

Memristors: Memristor with Ag‐Cluster‐Doped TiO2Films as Artificial Synapse for Neuroinspired Computing (Adv. Funct. Mater. 1/2018)

引用

Advanced Functional Materials 2018年第1期28卷

作者： Xiaobing Yan Jianhui Zhao Sen Liu Zhenyu Zhou Qi Liu Jingsheng Chen Xiang Yang Liu Key Laboratory of Optoelectronic Information Materials of Hebei Province Key Laboratory of Digital Medical Engineering of Hebei Province College of Electron and Information Engineering Hebei University Baoding 071002 P. R. China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 P. R. China Department of Materials Science and Engineering National University of Singapore 9 Engineering Drive 1 Singapore 117575 Singapore Department of Physics National University of Singapore 2 Science Drive 3 Singapore 117542 Singapore

来源：评论

学校读者我要写书评

暂无评论

A new static power clamp co-designed with input ESD protection circuit

A new static power clamp co-designed with input ESD protecti...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Jian Wang Jian Cao Guangyi Lu Xing Zhang Yuan Wang School of Software and Microelectronics Peking University Beijing China Peking University Beijing Beijing CN Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing China

ISBN: (纸本)9781467397209

A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and the excellent ESD performance.

关键词： Electrostatic discharges Clamps Logic gates Switching circuits Stress MOS devices Leakage currents

来源：评论

学校读者我要写书评

暂无评论

Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization

Deep Insights into Dielectric Breakdown in Tunnel FETs with ...

引用

IEEE International Electron devices Meeting

作者： Qianqian Huang Rundong Jia Jiadi Zhu Zhu Lv Jiaxin Wang Cheng Chen Yang Zhao Runsheng Wang Weihai Bu Wenbo Wang Jin Kang Kelu Hua Hanming Wu Shaofeng Yu Yangyuan Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Semiconductor Manufacturing International Corporation (SMIC) Shanghai 201203 and Beijing 100176 China

ISBN: (纸本)9781509039036

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

关键词： Tunnel FETs Awareness Reliability

来源：评论

学校读者我要写书评

暂无评论

A physics-based compact model for material- and operation-oriented switching behaviors of CBRAM

A physics-based compact model for material- and operation-or...

引用

International Electron devices Meeting (IEDM)

作者： Y. D. Zhao J. J. Hu P. Huang F. Yuan Y. Chai X. Y. Liu J. F. Kang Institute of Microelectronics Peking University Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Innovation Center for MicroNanoelectronics and Integrated System Beijing China Department of Applied Physics The Hong Kong Polytechnic University Hong Kong China

ISBN: (纸本)9781509039036

A physics-based compact model is developed to capture the essential resistive switching behaviors of conductive-bridge random access memory (CBRAM) under DC and AC operations. Three types of evolution modes of conductive filament correlated with material properties and operation schemes are modeled based on experimental observations. By modeling the temperature and electric-field effects as well as the electrical conduction, the model can well reproduce the DC and AC switching characteristics in different material stacks and operation modes. The calibrated model can be further implemented into SPICE to evaluate and optimize the array performance of CBRAM as a device-circuit-system co-design tool.

关键词： Mathematical model Switches Metals Oxidation Geometry Electric fields Data models

来源：评论

学校读者我要写书评

暂无评论

New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications

New Insights into the Near-Threshold Design in Nanoscale Fin...

引用

IEEE International Electron devices Meeting

作者： Xiaobo Jiang Shaofeng Guo Runsheng Wang Yuan Wang Xingsheng Wang Binjie Cheng Asen Asenov Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Synopsys 11 Somerset place Glasgow G3 7JT U.K

ISBN: (纸本)9781509039036

Energy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge - variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data. Significant improvements are achieved in the following three aspects: (1) Our newly proposed predictive compact variability models in all-region are accurately calibrated with experimental data, using a simple characterization method;(2) A new efficient approach for logic design space optimization is proposed based on a set of elaborately selected subthreshold FoMs, and the impacts of variation on energy efficiency, delay variation and failure probability are thoroughly investigated;(3) The conventional gate sizing method is also ameliorated specifically for FinFET NTV design. Based on silicon data, the proposed methodology is then demonstrated under V~(dd)=199mV and V_(dd)=145mV, targeting energy-efficiency priority and V_(dd) priority scenarios, respectively. This work provides helpful guidelines for FinFET variation-aware near-threshold design.

关键词： New Insights into Near-Threshold Design FinFET

来源：评论

学校读者我要写书评

暂无评论

Resistive Switching: Breaking the Current‐Retention Dilemma in Cation‐Based Resistive Switching devices Utilizing Graphene with Controlled Defects (Adv. Mater. 14/2018)

引用

Advanced Materials 2018年第14期30卷

作者： Xiaolong Zhao Jun Ma Xiangheng Xiao Qi Liu Lin Shao Di Chen Sen Liu Jiebin Niu Xumeng Zhang Yan Wang Rongrong Cao Wei Wang Zengfeng Di Hangbing Lv Shibing Long Ming Liu Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China Department of Physics Hubei Nuclear Solid Physics Key Laboratory and Center for Ion beam Application Wuhan University Wuhan 430072 China State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050 China School of Electronic Electrical and Communication Engineering University of Chinese Academy of Sciences Beijing 100049 China Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM) Nanjing 210009 China Department of Nuclear Engineering Texas A&M University College Station TX 77843 USA Materials Science and Technology Division Los Alamos National Laboratory Los Alamos NM 87545 USA

来源：评论

学校读者我要写书评

暂无评论

Effects of Si δ-Doping Condition and Growth Interruption on Electrical Properties of InP-Based High Electron Mobility Transistor Structures

引用

Chinese Physics Letters 2015年第9期32卷 112-115页

作者：周书星齐鸣艾立鹍徐安怀汪丽丹丁芃金智 State Key Laboratory of Functional Materials for lnformatics Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050 Microveave Devices and Integrated Circuits Department Key Laboratory of Microelectronics Device and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029

The InGaAs/InAIAs/InP high electron mobility transistor （HEM：F） structures with lattice-matched and pseudo- morphic channels are grown by gas source molecular beam epitaxy. Effects of Si ^-doping condition and growth interruption on the electrical properties are investigated by changing the Si-cell temperature, doping time and growth process. It is found that the optimal Si ^-doping concentration （Nd） is about 5.0 x 1012 cm-2 and the use of growth interruption has a dramatic effect on the improvement of electrical properties. The material structure and crystal interface are analyzed by secondary ion mass spectroscopy and high resolution transmission elec- tron microscopy. An InGaAs/InAiAs/InP HEMT device with a gate length of lOOnm is fabricated. The device presents good pinch-off characteristics and the kink-effect of the device is trifling. In addition, the device exhibits fT = 249 GHa and fmax 〉 400 GHz.

关键词： InP InGaAs Doping Condition and Growth Interruption on Electrical Properties of InP-Based High Electron Mobility Transistor Structures Effects of Si

来源：评论

学校读者我要写书评

暂无评论

Study on geometry of silicon PIN radiation detector for breakdown voltage improvement

Study on geometry of silicon PIN radiation detector for brea...

引用

作者： Liu, Hong-Zhi Yu, Min Shi, Bao-Hua Qi, Lin Wang, Shao-Nan Hu, An-Qi Du, Hong Wang, Jin-Yan Jin, Yu-Feng Yang, Bing National Key Laboratory of Nano/Micro Fabrication Technology Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing100871 China Department of Microelectronics College of Information Engineering North China University of Technology Beijing100144 China

The silicon PIN radiation detectors are always used under high working voltages. The breakdown voltage improvement has been researched in this paper. The resistivity of the silicon is larger than 20,000 Ω cm and the thickness is 1 mm. The field plate and field-limiting ring as well as round corners are applied for comprehensive improvement. The impact of field limiting ring distance to the main junction is tested by varying the ring distance from 30 μm to 260 μm. The simulation research on ring distance is carried out. The round corner radius is researched by varying the radius from 30 μm to 500 μm. Copyright © 2015 Inderscience Enterprises Ltd.

关键词： Electric breakdown

来源：评论

学校读者我要写书评

暂无评论

A Leakage Tolerant True Single-Phase Clock Dual-Modulus Prescaler Scheme

A Leakage Tolerant True Single-Phase Clock Dual-Modulus Pres...

引用

Asia-Pacific Microwave Conference

作者： Song Jia Ziyi Wang Shilin Yan Yuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

ISBN: (纸本)9781479987689

A new leakage-tolerant true single-phase clock dual-modulus prescaler based on a stage-merged scheme is presented. Leakage-restricting transistors are used to reduce the leakage currents at critical nodes and leakage-related malfunctions are eliminated at minimal cost in terms of speed, power and area overheads. An HSPICE simulation in a 40 nm process shows that the proposed divide-by-2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable to the performance levels of referenced designs.

关键词： Leakage currents Transistors Performance evaluation Clocks Phase locked loops Robustness Frequency conversion

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：