In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomica...
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In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 ***-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor (MOS) capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.
A novel architecture of high frequency resolution LC-tank based digitally controlled oscillator (DCO) is presented in this paper. The proposed architecture utilizes a differential tapped inductor and a capacitor array...
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ISBN:
(纸本)9781479983926
A novel architecture of high frequency resolution LC-tank based digitally controlled oscillator (DCO) is presented in this paper. The proposed architecture utilizes a differential tapped inductor and a capacitor array within the taps for fine frequency tuning. A prototype of 1.6 GHz DCO integrated in 0.18-μm CMOS technology exhibits a tuning range of 40.2% and a phase noise of -123.6 dBc/Hz@1MHz. With a minimal capacitance step of 7.5 fF, the frequency resolution is improved to 7.6 kHz/LSB. The DCO dissipates 3.2 mA from a 1.8 V supply and occupies an area of 0.46 mm 2 .
We present modeling and simulations of graphene coplanar waveguide(GCPW) under the frequency up to 50 GHz. Our simulation results show that the dimensions of GCPW greatly influence its insertion loss. In addition, dif...
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We present modeling and simulations of graphene coplanar waveguide(GCPW) under the frequency up to 50 GHz. Our simulation results show that the dimensions of GCPW greatly influence its insertion loss. In addition, different graphene layer numbers and structures of graphene-metal contact were also considered. We show that the usage of few-layer graphene and end-contact structure is able to decrease the insertion loss, which helps improve the radio-frequency performance of graphene coplanar waveguide.
A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel(FC),Peripheral Component Interconnect Express(PCIe),and RapidIO *** support multiple standards with a s...
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A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel(FC),Peripheral Component Interconnect Express(PCIe),and RapidIO *** support multiple standards with a single low power and low cost design,the transceiver presented here uses a wide swing range source-series-terminated(SST)transmitter(TX),a passive receiver(RX)equalizer,a dual-loop phase locked loop(PLL)and a mixed signal clock and data recovery(CDR)*** proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter,and a passive equalizer that achieves 4 dB transmission in the *** dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR’s reference.A CDR with a phase interpolator(PI)is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 *** transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 *** supply voltages of 1.2 V and 3.3 V,the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at3.125 Gb/s.
An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semic...
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An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is (110)〉(111) ~ (100), and the best channel direction is (110)/[110]. Moreover, the (110) device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while (100) and (111) devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.
Nitrogen plasma passivation (NPP) on (111) germanium (Ge) was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition (PECVD)....
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Nitrogen plasma passivation (NPP) on (111) germanium (Ge) was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition (PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness (EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its perform...
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ISBN:
(纸本)9781479983926
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33 dual modulus prescaler, a critical path cutting scheme is introduced to improve speed to the limit decided by the divide-by-4/5 unit.
A novel human body channel (HBC) energy harvesting scheme for body sensor networks (BSNs) is proposed in this paper. Human body channel is utilized innovatively as energy transmission medium to reduce the transmission...
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ISBN:
(纸本)9781479983926
A novel human body channel (HBC) energy harvesting scheme for body sensor networks (BSNs) is proposed in this paper. Human body channel is utilized innovatively as energy transmission medium to reduce the transmission loss dramatically and eliminate influence of shadow effect. Further, a high sensitivity and efficiency rectifier is presented by introducing an effective threshold compensation circuit. Experimental results of the energy harvesting scheme show that it can supply 2-μW power typically at -5 dBm transmitted power and up to 19.5-μW at +7 dBm transmitted power by 30 cm distance of human body channel. The sensitivity of the proposed rectifier is -22.5 dBm with 1-V output voltage. When offering 5-μA output current, the rectifier can achieve 25.87% efficiency. The rectifier is implemented in a standard 0.18-μm CMOS process and operating frequency is 145 MHz.
This paper presents a 0.5-2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic ...
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ISBN:
(纸本)9781479983926
This paper presents a 0.5-2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic power consumption is saved due to small filter switch size compared with parallel structures. Utilizing a tunable narrow band LNA in front of series N-path filter, 3rd harmonic rejection exceeding 54 dB with robust to process variation is realized. These techniques improve the front-end's adjacent and far-end frequency selectivity in RF domain, relaxing mixer's linearity design pressure. Implemented in 65 nm CMOS process, the frontend achieves a NF of 2.6-5.7 dB and maximum gain of 46-60 dB at 0.5-2 GHz, consuming 18-26 mW from 1.2 V voltage supply and occupies an area of 0.56 mm~2.
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