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共 429 条记录，以下是281-290 订阅

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Heavy-Ion-Induced Permanent Damage in Ultra-deep Submicron Fully Depleted SOI devices

Heavy-Ion-Induced Permanent Damage in Ultra-deep Submicron F...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Fei Tan Xia An Liangxi Huang Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467324748

In this paper,heavy-ion-induced permanent damage in fully depleted silicon-on-insulator（FD SOI） devices are *** exposure to heavy ions, the characteristics degradation of FD SOI nMOSFET are presented,which is due to the microdose effect in the oxide layer and the displacement damage in silicon ***,the measured results also exhibit strong device geometry *** electrical properties degradation such as the off-state leakage current and the on-state current become more serious with the gate length or gate width decreasing,which indicates that the heavy-ion-induced damage in ultra-deep submicron FD SOI devices can not be ignored and should be paid more attention for radiation hardened applications.

关键词： applications should serious

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An Innovative Sensing Architecture for Multilevel Flash Memory

An Innovative Sensing Architecture for Multilevel Flash Memo...

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Xiao-Min Gao Yuan Wang Yan-Dong He Gang-Gang Zhang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits(MoE) Institute of Microelectronics Peking University Beijing

ISBN: (纸本)9781467324748

Multilevel cell storage allows two or more bits to be stored in one cell,thus reducing almost 50% of Flash memory's area without technology shrinkage. Basic concepts like sensing schemes in multilevel Flash memory are fundamental and need further *** this paper,an innovative sensing architecture is presented,with the name of serial-parallel sensing scheme,which provides fast read speed and a medium area cost and power consumption,compared with conventional parallel and serial sensing *** 65nm technology,the new architecture performs well, almost five times as fast as serial sensing and has advantage over parallel sensing in both area and power consumption cost.

关键词： Multilevel storage,serial-parallel sensing architecture,sensing amplifier

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Analysis of the influence of contact position to the ESD protection ability in Ggnmos device

Analysis of the influence of contact position to the ESD pro...

引用

2nd International Conference of Electrical and Electronics Engineering, ICEEE 2011

作者： Zhang, Peng Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 Beijing China

ISBN: (纸本)9783642259043

For the silicided GGnMOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, ballasting resistance is introduced to allow a more uniform current distribution. How the drain contact to gate spacing and contact to contact spacing influencing the ESD performance of the GGnMOS is investigated. We find that lengthening the contact to contact spacing can significantly improve the ESD performance of silicided GGnMOS. © 2011 Springer-Verlag.

关键词： Electrostatic devices

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A novel multi-finger layout strategy for GGnMOS ESD protection device

A novel multi-finger layout strategy for GGnMOS ESD protecti...

引用

2011 IEEE 9th International Conference on ASIC, ASICON 2011

作者： Zhang, Peng Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781612841908

A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniformity turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS). The multi-finger gates as well as drains and sources are connected in serrate type. The whole multi-finger device acts as singer finger with large gate width. After realized in 0.13μm craft and tested under TLP method, the It2 per unit channel width of the novel GGnMOSs are much higher than those of the traditional GGnMOSs by this simply approach. © 2011 IEEE.

关键词： Integrated circuits

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Effective design for crff sigma-delta modulators using inverters based on 0.13μm CMOS

Effective design for crff sigma-delta modulators using inver...

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作者： Li, Hongyi Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9783642197116

In this paper, an efficient method to relax timing requirements of CRFF sigma-delta modulators has been proposed. A system optimization to circuit level design was finished. Class-C inverter was used to realize half delay integrators of the proposed structure. A 4th-order 1-bit CRFF topology was implemented in smic 0.13μm CMOS technology. With 31.25MHz sampling frequency and 64x oversampling ratio, 13.2-bit resolution has been reached. The whole circuit consumes 472.63-μW power from a single 0.6V supply voltage. Thus, a low-voltage low-power medium-bandwidth high-accuracy sigma-delta modulator has been obtained. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： Topology

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Analysis of the Influence of Contact Position to the ESD Protection Ability in Ggnmos Device

Analysis of the Influence of Contact Position to the ESD Pro...

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The second International Conference of Electrical and Electronics Engineering(ICEEE 2011)

作者： Peng Zhang Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

For the silicided GGn MOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, ballasting resistance is introduced to allow a more uniform current distribution. How the drain contact to gate spacing and contact to contact spacing influencing the ESD performance of the GGn MOS is investigated. We find that lengthening the contact to contact spacing can significantly improve the ESD performance of silicided GGn MOS.

关键词： Contact Spacing,Current Localization,Ballasting Resistance,Second Breakdown Current,ESD,Multi-finger GGn MOS

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An extensible drive system for AM-OLED panel

An extensible drive system for AM-OLED panel

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IEEE Conference on Electron devices and Solid-State circuits

作者： Lilan Yu Wengao Lu Guannan Wang Yacong Zhang Ze Huang Zhongjian Chen Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics Peking University Beijing China

A drive system for active-matrix OLED panel is presented. The developed system comprises a digital interface which can receive DVI or MCU signals directly, a digital control part, a SRAM for storing display information, common drivers, and the 64-step gray scale segment drivers. Both common driver and segment driver is capable to be cascaded, so it can drive panels in different resolutions by using multiple chips. The drivers are using 0.35 um CMOS technology with 15V high voltage devices.

关键词： Organic light emitting diodes Vehicles Layout Random access memory Simulation Active matrix technology microelectronics

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A small-area low-mismatch multi-channel constant current LED driver

A small-area low-mismatch multi-channel constant current LED...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Ze Huang Wengao Lu Lilan Yu Guannan Wang Xiangyun Meng Yacong Zhang Zhongjian Chen Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics Peking University Beijing China

This paper proposes a new structure of LED(Light-emitting diode) driver for obtaining a low mismatch output current between different channels and even reduces the chip area. It's fabricated with TSMC 0.35 μm DDD process. The chip contains 16 channels and the maximum/minimum output current is 3mA/45mA, respectively. The value of each channel's output current is the same and controlled by a programmable 6-bits digital input signals. The circuit uses constant gate voltage of the power MOS working in the linear region whose (V GS - V TH ) is 10 to 50 times of V DS . The advantage is no DAC(Digital-to-Analog Converter) and no complex gate voltage generating circuit. Simple gate voltage generating circuit can also adapt to a wide range of external resistance changes. Because of the lower mismatch caused by threshold voltage mismatch, it can achieve a highly matched output current. The chip has only ±1.1% mismatch between different channels. The area of each channel's power MOS is only 200 μm × 100 μm. The area of analog part including current bias, bandgap reference, current mirror, and other control circuits is only 400 μm × 200 μm.

关键词： Light emitting diodes Logic gates Generators Mirrors Threshold voltage Resistors Driver circuits

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A novel on-chip CMOS current sensor implemented by switched capacitors for a current-mode control DC-DC buck converter

A novel on-chip CMOS current sensor implemented by switched ...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Yong Zhang Wengao Lu Juan Guo Yajing Zhang Zhongjian Chen Yacong Zhang Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

A novel on-chip CMOS current sensor implemented by switched capacitors for a current - mode buck converter is presented in this paper. This proposed current sensing circuit does not need another sense MOSFET and a voltage-to-current and current-to-voltage transform circuit. We use the 0.35um DPTM CMOS process to design and simulate this circuit. Test result shows that the accuracy and the speed of the proposed current sensing circuit are high.

关键词： Sensors Capacitors Power MOSFET Accuracy CMOS integrated circuits Resistors

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A low power high speed readout circuit for 320×320 IRFPA

A low power high speed readout circuit for 320×320 IRFPA

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IEEE Conference on Electron devices and Solid-State circuits

作者： Guannan Wang Wengao Lu Ran Fang Li You Yacong Zhang Zhongjian Chen Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffer's power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSA's feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 × 320 ROIC with pixel size of 30 × 30 μm 2 has been designed and fabricated with a 0.35 μm DPTM CMOS process under 5v supply voltage.

关键词： Capacitors Capacitance Power dissipation Arrays MOSFETs Buffer storage Noise

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