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An Implantable Readout Circuit with On-Chip Reference Buffer for the Detection of Biological Electrical Signals Employing Artificial Intelligence Algorithms to Compensate and Calibrate 3

An Implantable Readout Circuit with On-Chip Reference Buffer...

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3rd International Conference on Artificial Intelligence and Advanced Manufacture, AIAM 2021

作者： Zhou, Fei Zhang, Yacong Zhu, Runkun School of Software and Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics Peking University Beijing China

ISBN: (纸本)9781450385046

This paper proposes an implantable readout circuit with on-chip reference voltage. Meanwhile, artificial intelligence algorithms are used to dynamically adjust the calibration and signal processing of the circuit. In the reference buffer block, in order to avoid the voltage reference drifting due to excessive load, an offset compensation DAC with current provided by internal current source is applied to solve the problem of drawing current from voltage reference. Moreover, a low-dropout (LDO) regulator with improved transient responses is proposed to provide voltage reference for driving the successive approximation register (SAR) analog-to-digital converter (ADC) capacitor array. In the digital control block, through the processing of artificial intelligence algorithms, the performance of the entire circuit has been significantly improved. The readout circuit is implemented in standard 180-nm 1.8V/5V CMOS process. The LDO achieves only a 5.4μW static power consumption in the ADC conversion process. The power consumption of the bandgap reference circuit, bias buffer and LDO is 12.6μW, leading to a 57.2μW total power cost for the readout circuit. The digital calibration algorithm makes the ENOB of SAR ADC reaches 9.78. © 2021 ACM.

关键词： Timing circuits

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A Low Power Active-Passive Noise Shaping SAR ADC 3

A Low Power Active-Passive Noise Shaping SAR ADC

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3rd IEEE International Conference on Electronic Technology, Communication and Information, ICETCI 2023

作者： Huang, Ziqi Xu, Weilin Wei, Baolin Wei, Xueming Li, Haiou Guilin University of Electronic Science and Technology Guangxi Key Laboratory of Precision Navigation Technology and Applications Guilin China Guilin University of Electronic Technology Key Laboratory of Microelectronic Devices and Integrated Circuits Education Department of Guangxi Zhuang Autonomous Region Guilin China

ISBN: (纸本)9798350398410

The traditional passive noise-shaping SAR ADC has low power consumption but weak shaping capability;while the active noise-shaping SAR ADC has strong shaping capability but high-power consumption. The typical active-passive SAR ADC still consumes considerable power due to the use of OTA amplifier in the active part. In this paper, an active-passive noise-shaping SAR ADC is designed by using floating inversion amplifier (FIA) to replace the traditional OTA amplifier in the active part, which achieves a strong noise shaping capability and low power consumption at the same time. The second-order active-passive noise-shaping SAR ADC circuit designed by a 180nm CMOS process achieves 14.6-bit ENOB with 400KS/s sampling rate and consumes only 28.9μW. © 2023 IEEE.

关键词： Electric power utilization

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A Low Power OTA-C Filter for Wireless Body Area Networks 8

A Low Power OTA-C Filter for Wireless Body Area Networks

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8th International Conference on Integrated circuits and Microsystems, ICICM 2023

作者： Zhu, Jueyong Xu, Weilin Wei, Xueming Wei, Baolin Li, Haiou Guilin University of Electronic Technology Key Laboratory of Microelectronic Devices and Integrated Circuits Education Department of Guangxi Zhuang Autonomous Region Guilin China Guilin University of Electronic Science and Technology Guangxi Key Laboratory of Precision Navigation Technology and Applications Guilin China

ISBN: (纸本)9798350318517

The traditional OTA structure uses the current splitting technology to decompose most of the current, which can effectively reduce the transconductance, but the excessive current splitting ratio will bring power loss. To solve this problem, a multiple-output fully differential (MOFD) cascode OTA structure is proposed. This structure can generate additional output by connecting the load to the current splitting branch, which can effectively utilize the current generated by the current splitting to reduce the power loss. In order to reduce the passband attenuation of the filter, the output stage adopts the cascode structure to increase the output impedance of the OTA, and the improved source negative feedback structure obtains lower transconductance and better linear range. Compared with the traditional structure, the number of OTAs of the fifth-order Butterworth low-pass filter with this OTA structure is reduced from 11 to 6, thereby reducing power consumption and achieving lower passband attenuation. The circuit is verified by 0.18 um CMOS process. The results show that the passband gain of the proposed filter is only -6.1 dB. -3dB frequency is 260 Hz. For 100 mV sinusoidal input signal at 50 Hz, the total harmonic distortion (THD) of the filter is about -66 dB and the power consumption is only 11.4 μ W at 1.8 V supply. © 2023 IEEE.

关键词： Low pass filters

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A CMOS Time-of-Flight Image Sensor with High Dynamic Range Digital Pixel 14

A CMOS Time-of-Flight Image Sensor with High Dynamic Range D...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Yu, Shanzhe Zhang, Yacong Zhou, Fei Lu, Wengao Lei, Shuyu Chen, Zhongjian Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China ABAX Sensing Electronic Technology Ningbo China

ISBN: (纸本)9781665411493

To widen measuring range and suppress background light, a CMOS time-of-flight image sensor with high dynamic range digital pixel is proposed. The sensing charge is quantized by extended-counting analogue-to-digital converter (ADC) which consists of pixel coarse quantization and column fine quantization. To maximize dynamic range in limited pixel area, the coarse quantization circuit is shared by 2×2 pixels, in which a novel up/down counter with a small number of transistors is proposed. Based on the pixel circuit, a 32×32 prototype TOF imager with 12μm-pitch digital pixel is designed in 0.11μm 1P4M CMOS image sensor technology. Simulation results show that a 104.6dB dynamic range of this ADC for wide measuring range is achieved at a frame rate of 50Hz. © 2021 IEEE.

关键词： Image sensors

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Flexible Hf_(0.5)Zr_(0.5)O_(2)ferroelectric thin films on polyimide with improved ferroelectricity and high flexibility

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Nano Research 2022年第4期15卷 2913-2918页

作者： Yuting Chen Yang Yang Peng Yuan Pengfei Jiang Yuan Wang Yannan Xu Shuxian Lv Yaxin Ding Zhiwei Dang Zhaomeng Gao Tiancheng Gong Yan Wang Qing Luo Key Laboratory of Microelectronic Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100049China Department of Mathematics and Theories Peng Cheng LaboratoryNo.2Xingke 1st StreetNanshanShenzhen 518000China

Flexible memory devices are promising for information storage and data processing applications in portable,wearable,and smart electronics operating under curved *** this work,we realized high-performance flexible ferroelectric capacitors based on Hf_(0.5)Zr_(0.5)O_(2)(HZO)thin film by depositing a buffer layer of Al_(2)O_(3)on polyimide(PI)substrates using atomic layer deposition(ALD).The flexible ferroelectric HZO films exhibit high remnant polarization(Pr)of 21μC/cm^(2).Furthermore,deterioration of polarization,retention,and endurance performance was not observed even at a bending radius of 2 mm after 5,000 bending *** work marks a critical step in the development of high-performance flexible HfO_(2)-based ferroelectric memories for next-generation wearable electronic devices.

关键词： ferroelectric Hf_(0.5)Zr_(0.5)O_(2)(HZO) Al_(2)O_(3)buffer layer flexible

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Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2Bi-Layer Dipole-First Process Using PVD Method for Advanced IC Technology

Experimental Investigation of Ultra-Low Temperature LA2O3/HF...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Wei, Yanzhao Yao, Jiaxin Xu, Renren Zhang, Qingzhu Yin, Huaxiang Chinese Academy of Sciences Integrated Circuit Advanced Process R&d Center Institute of Microelectronics Beijing100029 China Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronic Devices and Integrated Technology Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

ISBN: (纸本)9798350311006

In this paper, a La2O3/HfO2 bi-layer dipole-first (DF) process is proposed and investigated by ultra-low temperature PVD dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3D-IC (M3D) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (VFB) negatively shifts 60 mV with sub-1nm La2O3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (Dit) are suppressed by La2O3/HfO2 bi-layer DF process to improve device performance. These results exhibit a promising bi-layer DF process in low thermal integration for advanced IC technology. © 2023 IEEE.

关键词： Timing circuits

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An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applications

An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applicat...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Zhaotong Zhang Yi Zhong Yingying Cui Yawei Ding Yukun Xue Qibin Li Ruining Yang Jian Cao Yuan Wang Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center School of Integrated Circuits Peking University School of Software and Microelectronics Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Inspired by the brain, Spiking Neural Network (SNN) applies temporally sparse spiking communication to gain more bio-mimetic and highly energy efficient computing. The current mainstream platforms for SNN applications are typically the combination of Host+FPGA+Chip Array, which requires an efficient host to preprocess and encode data. It’s not suitable for end-to-end tasks in edge due to its high system power consumption of host and non-negligible high latency of protocol conversion on FPGA. In addition, Convolutional Neural Network (CNN), exhibits strong feature extraction capabilities. Like the brain's visual system, a hierarchical CNN-SNN hybrid network, in which SNN can make use of CNN’s feature extraction capabilities during encoding, can achieve better performance. In this study, we design a 64Neural-Core Array and integrate it with a CNN encoder and a low-power RISC-V CPU within a System-on-Chip (SoC) to enable comprehensive end-to-end hybrid network application support. The proposed heterogeneous SoC is implemented on a Virtex UltraScale+ XCVU9P FPGA, featuring 32.8K neurons, 37.7M synapses and 578GOPS/s peak performance. It processes MNIST classification with a peak throughput of 2022 images per second at frequency of 250MHz. This design gains a balance between high throughput and recognition accuracy simultaneously.

关键词： Accuracy Visual systems Feature extraction Throughput Encoding System-on-chip Convolutional neural networks

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Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies

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Journal of Semiconductors 2025年第6期46卷 66-78页

作者： Yu Song Pengfei Jiang Pan Xu Xueyang Peng Qianqian Wei Qingyi Yan Wei Wei Yuan Wang Xiao Long Tiancheng Gong Yang Yang Eskilla Venkata Ramana Qing Luo Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of SciencesBeijing 100029China Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 101408China I3N-Aveiro Department of PhysicsUniversity of AveiroAveiro3810193Portugal

The novel HfO2-based ferroelectric field effect transistor(FeFET)is considered a promising candidate for next-genera-tion nonvolatile memory(NVM).However,a series of reliability issues caused by the fatigue effect hinder its further ***,a comprehensive understanding of the fatigue mechanisms of the device and optimization strategies is essen-tial for its *** fundamental mechanism of the fatigue effect is attributed to charge trapping and trap generation based on the current studies,and the underlying causes,occurrence locations and specific impacts are analyzed in this *** particular,the asymmetric trapping/detrapping of electrons and holes,as well as the relationship between the ferroelectric(FE)polarization and charge trapping,are given particular *** categorizing and summarizing the current progress,we propose a series of optimization strategies derived based on the fatigue mechanisms.

关键词： FeFET fatigue charge trapping trap generation

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An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow

An Energy-Efficient Differential Frame Convolutional Acceler...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Zhenhui Dai Jiawei Wang Yi Zhong Kunyu Feng Cheng Zhao Yuanyuan Jiang Peiyu Chen Yuan Wang Dunshan Yu Xiaoxin Cui School of Integrated Circuits Peking University Beijing Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center Peking University Beijing School of Software and Microelectronics Peking University Beijing Beijing Advanced Innovation Center for Integrated Circuits Beijing

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Convolutional neural networks require a huge amount of computation in video applications. For some specific tasks, such as surveillance, differential frame convolution reuses inter-frame data and significantly reduces multiplication and accumulation. However, there are still some challenges in improving energy efficiency of differential frame convolution on chips. Firstly, differential frame convolution brings additional on-chip storage for reusing inter-frame data. Secondly, in post-processing of differential frame convolution, there are more memory accessing and arithmetic logic operations. Therefore, sparse working mode is of vital importance for the post-processing. In response to these challenges, this work proposes an on-chip fusion storage architecture for energy-efficient differential frame convolution and a pixel-level pipeline data flow that supports the sparsity of features. The simulation of our accelerator implemented in 28nm CMOS can achieve energy efficiency by 3.09× compared with other state-of-the-art works

关键词： Convolution Surveillance Pipelines Computer architecture Energy efficiency System-on-chip Convolutional neural networks

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Improvement of RRAM Uniformity and Analog Characteristics through Localized Metal Doping

Improvement of RRAM Uniformity and Analog Characteristics th...

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2021 China Semiconductor Technology International Conference, CSTIC 2021

作者： Qin, Yabo Wang, Zongwei Chen, Qingyu Ling, Yaotian Wu, Lindong Cai, Yimao Huang, Ru Institute of Microelectronics Peking University Beijing100871 China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing100871 China

ISBN: (纸本)9781665449458

In this work, the influence of localized metal ion doping on the uniformity and analog behavior in TaOx-based RRAM is investigated. Experimental results show that Al ion local doping can improve the uniformity. The distributions of set/reset voltage and LRS/HRS become tighter. Moreover, the TaOx-based RRAM with Al doping shows excellent analog switching behaviors compared with the device without doping. The underlying mechanism may be explained by the reduced formation energy of oxygen vacancies and relayed traps in the doped area, which makes it easier to form incremental conductive filaments in the regions with high ion doping concentration. © 2021 IEEE.

关键词： RRAM

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