In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si （110） nanowire via the simulation of strain distribution and the calculation of a genera...
详细信息
In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si （110） nanowire via the simulation of strain distribution and the calculation of a generalized 6 × 6k .p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO2 insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO2 insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO2 insulator, the strain of the HfO2 gate insulator in Si （110） nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO2 insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design.
Low power on-chip interconnect technique is important for deep submicron SOC design. In this paper, a novel low swing drivers scheme based on charge redistribution is proposed. Significant reduction in power dissipati...
详细信息
Low power on-chip interconnect technique is important for deep submicron SOC design. In this paper, a novel low swing drivers scheme based on charge redistribution is proposed. Significant reduction in power dissipation is achieved by dividing the full signal swing into several lower ones. The proposed circuits are especially suitable for driving multi-branch transmission wires by utilizing higher efficiency of charges. Compared with the reference design, the new scheme can reduce power dissipation by more than 66% as shown by HSPICE simulation while driving three branches. The proposed circuits have been fabricated and its effectiveness has been verified by measurement results.
In this paper, two high-resolution mediumbandwidth single-loop 4 th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The ove...
详细信息
This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zer...
详细信息
ISBN:
(纸本)9781424467372
This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-μm CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.
In this paper, a novel design method has been proposed to realize feed-forward low-distortion unity STF sigma-delta modulators which are the critical blocks in multi-loop SMASH structure. Using the method, a timing-re...
详细信息
This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to ...
详细信息
In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been pro...
详细信息
ISBN:
(纸本)9781424467372
In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction. Second, a flexible SMASH 2-2 has been proposed to choose appropriate coefficients for different requirements. Third, a SMASH 2-2 with feed-forward quantization noise self-coupled structure has been displayed to cancel quantization error of the preceding stage totally. Detailed simulation results and comparisons demonstrate the performance of these topologies.
A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and...
详细信息
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quas...
详细信息
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic pr...
详细信息
暂无评论