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Pulse voltage dependent resistive switching behaviors of HfO 2-based RRAM

Pulse voltage dependent resistive switching behaviors of HfO...

引用

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Gao, Bin Chen, Bing Chen, Yuansha Liu, Lifeng Liu, Xiaoyan Han, Ruqi Kang, Jinfeng Institute of Microelectronics Peking University Key Laboratory of Microelectronic Devices and Circuits Beijing 100871 China

ISBN: (纸本)9781424457984

Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can be improved. Voltage pulse controlled resistance states were observed. This behavior may provide the new application with the new function circuits. ©2010 IEEE.

关键词： RRAM

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Impacts of diameter-dependent annealing on S/D extension random dopant fluctuations in silicon nanowire MOSFETs

Impacts of diameter-dependent annealing on S/D extension ran...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Yu, Tao Wang, Runsheng Ding, Wei Huang, Ru Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457984

In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSD variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSD dominates that of ON current. The tradeoff between RSD and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs. ©2010 IEEE.

关键词： Threshold voltage

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A novel nitrogen-doped SiOx resistive switching memory with low switching voltages

A novel nitrogen-doped SiOx resistive switching memory with ...

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2010 15th Silicon Nanoelectronics Workshop, SNW 2010

作者： Gao, Dejin Zhang, Lijie Huang, Ru Wang, Runsheng Wu, Dongmei Kuang, Yongbian Tang, Yu Yu, Zhe Wang, Albert Z. H. Wang, Yangyuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China Dept. of Electrical Engineering University of California Riverside CA 92521 United States

ISBN: (纸本)9781424477272

In summary, a novel RRAM with the structure of Cu/SixO yNz/W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demonstrating its potential for low-power applications. Repeatable unipolar resistive switching characteristics in terms of high off/on resistance ratio and good retention capability were observed. The switching mechanism of the device was analyzed and can be explained by the formation and rupture of vacancy-filaments.

关键词： Nitrogen

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An efficient approach to improve PSRR performance of kuijk BGR topology

An efficient approach to improve PSRR performance of kuijk B...

引用

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Nie, Hui Lu, Wengao Fang, Ran Wang, Guannan Zhang, Yacong Chen, Zhongjian Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking University Beijing 100871 China School of Software and Microelectronics Peking University Beijing 102600 China

ISBN: (纸本)9781424457984

A highly efficient approach to improve PSRR behavior of Kuijk BGR topology is derived though small signal transfer function analysis and, a BGR circuit has been designed and fabricated on standard 0.5μm CMOS technology to verify this method. This thought greatly relieves the trade-offs of BGR circuit design among power consumption, PSRR performance, area and etc.. This BGR circuit consumes 3μA current at 5V single power supply, with >130 dB DC PSRR performance, occupies an area of 350μmx100μm, and is of self-biased characteristic with 2∼6 V work supply voltage range. ©2010 IEEE.

关键词： Topology

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An Efficient Approach to Improve PSRR Performance of Kuijk BGR Topology

An Efficient Approach to Improve PSRR Performance of Kuijk B...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Hui Nie Lijiu Ji Zhongjian Chen Ran Fang Wengao Lu Guannan Wang Yacong Zhang Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking Univer Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking Univer Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking Univers

A highly efficient approach to improve PSRR behavior of Kuijk BGR topology is derived though small signal transfer function analysis and, a BGR circuit has been designed and fabricated on standard 0.5μm CMOS technology to verify this method. This thought greatly relieves the trade-offs of BGR circuit design among power consumption, PSRR performance, area and etc.. This BGR circuit consumes 3μA current at 5V single power supply, with >130 dB DC PSRR performance, occupies an area of 350μm100um, and is of selfbiased characteristic with 2~6 V work supply voltage range.

关键词： Topology Power supplies Poles and zeros Simulation Photonic band gap Frequency estimation Network topology

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New observations of suppressed randomization in LER/LWR of Si nanowire transistors: Experiments and mechanism analysis

New observations of suppressed randomization in LER/LWR of S...

引用

International Electron devices Meeting (IEDM)

作者： Runsheng Wang Tao Yu Ru Huang Yujie Ai Shuangshuang Pu Zhihua Hao Jing Zhuge Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, the nanowire (NW) line-edge/width roughness (LER/LWR) effects in Si nanowire transistors (SNWTs) are investigated by both experiments and theoretical analysis. New LER/LWR characteristics are first observed in SNWTs, which exhibits suppressed randomization and enhanced systematic variation, rather than pure random LER/LWR in planar and FinFET devices. An improved characterization method is proposed to distinguish the random and systematic variation components in NW LER/LWR. For the first time, the effects of the key fabrication process on the NW LWR are studied in detail, including impacts of different oxidation temperature, NW channel orientations, and patterning techniques (hardmask trimming, spacer define and E-beam lithography). The results indicate that the spacer define method combined with self-limiting oxidation is beneficial for SNWTs. The mechanism of reducing the random variation in NW LER/LWR is analyzed, considering 2-D stress-retarded curvature-dependent oxidation. Taken into account the variation of quantum confined carrier profile, a physical device model is also developed, providing some guidelines for LER/LWR-hardening design of SNWTs.

关键词： Oxidation Systematics Correlation Silicon Degradation Temperature Temperature measurement

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Two Effective Single-Loop High-Performance Sigma-Delta Modulators Based on 0.13μm CMOS

Two Effective Single-Loop High-Performance Sigma-Delta Modul...

引用

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Hongyi Li Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After simulation, under the same circuit conditions, feedback structure gives better performance than feed-forward one. The experiment result could be a useful reference for the topology choice.

关键词： sigma-delta modulator switch-capacitor (SC) integrator feedback topology feed-forward topology high-resolution

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A clock and data recovery circuit for 3.125Gb/s RapidIO SerDes

A clock and data recovery circuit for 3.125Gb/s RapidIO SerD...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Zhao Zhihui Wang Yuan Zhao Junlei Yang Hailing Jia Song Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to lessen the problems in routing high speed clocks and reduce power. An improved half rate bang-bang phase detector is presented to assure the stability of the system. Moreover, the paper proposes a simplified control scheme for the phase interpolator to further reduce power and cost. The CDR takes an area of less than 0.05 m m 2 , and post simulation shows that the CDR has a RMS jitter of UI pp /32 (11.4 ps @3.125GBaud) and consumes 9.5 mW at 3.125 GBaud.

关键词： Bandwidth Clocks Jitter

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Improved multi-loop SMASH sigma-delta modulator for wideband applications

Improved multi-loop SMASH sigma-delta modulator for wideband...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Hongyi Li Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, a novel design method has been proposed to realize feed-forward low-distortion unity STF sigma-delta modulators which are the critical blocks in multi-loop SMASH structure. Using the method, a timing-relaxed stable unity STF 2nd-order modulator has been proposed in detail. After that, an extremely high-resolution SMASH 2(3b)-2(3b)-1(2b) has been suggested using the proposed stages. Extensive results prove the efficiency of this topology.

关键词： Switches Wideband Computer languages

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Simulation of line-edge roughness effects in silicon nanowire MOSFETs

Simulation of line-edge roughness effects in silicon nanowir...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Tao Yu Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, the effects of nanowire (NW) line-edge roughness (LER) in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) are investigated by 3-D statistical simulation in terms of both performance variation and mean value degradation. A physical model is developed for NW LER induced performance degradation in SNWTs for the first time. The results indicate large performance mean value degradations due to NW LER in SNWTs. However, the LER induced parameter variation is still acceptable. In addition, as the LER correlation length (Λ) scales beyond the gate length, new distribution of performance parameters is observed, which has dual-peaks rather than single in conventional Gaussian distribution. The optimization for NW LER parameters is given for SNWT design as well.

关键词： Logic gates Degradation Silicon Performance evaluation MOSFETs Integrated circuit modeling Solid modeling

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