This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only...
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This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.
A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference direct...
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A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.
A CMOS ASIC has been designed and implemented for readout and control of MEMS vibratory gyroscopes. A low noise design is achieved by using the technique of sinusoidal chopper stabilization with a chopping frequency o...
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ISBN:
(纸本)9781424457977
A CMOS ASIC has been designed and implemented for readout and control of MEMS vibratory gyroscopes. A low noise design is achieved by using the technique of sinusoidal chopper stabilization with a chopping frequency of 2MHz, which will effectively suppress the low frequency noise. A closed loop control method in driving mode is presented. The Chip is fabricated in a 0.35μm standard CMOS process with an area of 2.5×2.5mm2. The test is performed with a vibratory gyroscope on the condition of closed-loop control, and the measurement result shows a detecting resolution of 6aF in 100Hz bandwidth from a single 5V supply.
A readout integrated circuit for high energy particle detectors is presented. The circuit designed is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper with four selectable peaking time, and an output sta...
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In this paper, we demonstrate a Monte Carlo simulator for ambipolar Schottky barrier MOSFETs which includes tunneling and thermal emission of electrons and holes and the appropriate treatment of carrier transport at n...
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Design of a CMOS readout circuit for 160x120 format microcantilever infrared FPAs with snapshot integration is presented in this paper. The pixel pitch is 50m and capacitive trans-impedance amplifier is used in pixel ...
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A readout integrated circuit (ROIC) for uncooled microcantilever infrared focal plane arrays (IRFPAs) based on capacitive readout is proposed. The ROIC is optimized according to noise modeling and analysis to reduce n...
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Double gate SBFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET are simulated. A comparative study between them is made. We have found that the DG-ASBFET is more appropriate for LOP and LS...
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In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress ind...
In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress induces an annealing effect by removing part of the radiation-induced positive charges. If we choose a relatively low temperature to avoid the annealing effect, a remarkable radiation acceleration effect on device degradation is observed and the lifetime of pMOSFETs significantly reduces due to more radiation-induced new hole traps in the oxide. However, the acceleration effect seems independent of the oxide electric field during NBT stress. The work in this paper indicates that it is important to choose proper NBT stress conditions if we use NBTI to predict the lifetime of the pMOSFETs which operate in the radiation environments.
The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most effici...
The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most efficient in improving the driving current and RF performance of n-SNWTs under the same stress value. In addition, the transverse compressive strain is also beneficial to the performance improvement, and can be combined in the stress engineering. Particularly, transverse biaxial compressive strain can effectively enhance the driving current, and at the same time slightly decrease the off-current of n-SNWT, which is beneficial for high speed and low power design. The results indicate that, due to the unique feature of gate-all-around 1D structure, the strain design in SNWTs, especially the combination of longitudinal strain and transverse strain, can be specially optimized for better device performance.
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