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Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology

Experimental investigation and design optimization guideline...

引用

International Electron devices Meeting (IEDM)

作者： Jing Zhuge Runsheng Wang Ru Huang Jibin Zou Xin Huang D.-W. Kim Donggun Park Xing Zhang Yangyuan Wang Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Beijing China Device Research Team Samsung Electronics Company Limited Kyunggi South Korea

ISBN: (纸本)9781424456390

In this paper, the characteristic variability in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) is experimentally studied. Variation sources in SNWTs are extracted for the first time, taking into account the strongly-confined geometry induced quantum effect, quasi-ballistic effects, as well as the parasitic quantum resistance at the interface of 1D channel and 3D wide S/D regions. The measured results show that with suppressed random dopant fluctuations (RDF) in the intrinsic channel, variations in radius (R) and metal-gate work function (WF) of SNWTs dominate both the threshold voltage and on-current fluctuations, and line-edge-roughness (LER) shows minor impact. The influence of the SNWT variation sources on SRAM performance is estimated and compared with planar devices. In addition to process variation, variation induced by random telegraph signal (RTS) noise in SNWTs is also investigated for the evaluation of SRAM cell operating window. Design optimization guidelines are given based on the SRAM variation analyzed results.

关键词： CMOS technology Design optimization Guidelines Silicon Random access memory Fluctuations MOSFETs Geometry Electrical resistance measurement Resource description framework

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An analytic model of the silicon-based nanowire Schottky Barrier MOSFET

An analytic model of the silicon-based nanowire Schottky Bar...

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作者： Zhou, Xingye Che, Yuchi Zhang, Lining He, Jin Chan, Mansun Key Laboratory of Integrated Microsystems Micro and Nano Electronic Device and Integrated Technology Center Shenzhen Graduate School of Peking University Shenzhen 518055 China Key Laboratory of Microelectronic Devices and Circuits of Ministry of Education School of Electronics Engineering and Computer Science Peking University 100871 China Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Clearwater Bay Kowloon Hong Kong

ISBN: (纸本)9781439817841

In this paper, an analytic model of the Silicon-based Nanowire Schottky-Barrier MOSFETs is developed based on the 2D solution of body potential together with the WKB tunneling theory. The proposed model predicts the electrical characteristics of the silicon-based nanowire Schottky barrier MOSFETs with different geometry and structure parameters and extensive comparisons with the 2-D numerical simulation show that the presented model is valid for all operation regions of such a device with a variety of geometry parameters and different work function configurations of the metal source (drain). Such a compact model may be useful for us to benchmark nanowire Schottky barrier MOSFET circuit performance and device structure optimization.

关键词： Nanowires

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A Web-Based Platform for Nanoscale Non-classical Device Modeling and Circuit Performance Simulation

A Web-Based Platform for Nanoscale Non-classical Device Mode...

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International Conference on Web Information Systems and Mining (WISM)

作者： Hao Zhuang Frank He Xinnan Lin Lining Zhang Jian Zhang Xiufang Zhang Mansun Chan Research Center of Micro-& Nano-Device and Technology The Key Laboratory of Integrated Microsystems Shenzhen Graduate School Peking University Shenzhen China TSRC Key Laboratory of Microelectronic Devices and Circuits of Chinese Ministry of Education Peking University Beijing China Department of Electronic & Computer Engineering Hong Kong University of Science and Technology Hong Kong China

This paper describes a web-based platform for nanoscale non-classical device modeling and circuit simulation, especially for non-classical CMOS device compact modeling and circuit performance prediction. This platform is based on program libraries, including model code files. We use SPICE as circuit simulation framework, and the Verilog-A as model design language. Based on the user input deck content, running embedding device and circuit programs, the platform produces several types of device characteristics output such as data texts and graphs on the web page for analysis, according to the simulation results and users' requests. Some nanoscale device modeling examples and the circuit simulation cases are demonstrated by the means of the platform configures and function application. It is shown that not only does this kind of platform address problems arising from the dependence on computer operating system of modeling and simulation software, the complexity of software and program update, but also helps researchers focus on their research on device physics and circuit design, display their research results and share latest research achievements or new technology online, which will accelerate the development of device modeling and circuit design technology in turn.

关键词： Nanoscale devices Circuit optimization Circuit simulation Semiconductor device modeling Predictive models Computational modeling Circuit synthesis Libraries SPICE Hardware design languages

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A novel calibration technique applying to an adaptive-bandwidth PLL

A novel calibration technique applying to an adaptive-bandwi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Ying, Song Yuan, Wang Song, Jia Baoying, Zhao Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL. The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly. The maximum calibration time is less than five comparison periods. With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole working range. The proposed circuit has been implemented in 0.18um CMOS logic process. Results show that the calibration time is less than 1.2s, and the total locking time is less than 3s. The PLL has good jitter performance within its operating range from 860MHz to 2.1GHz. © 2008 IEEE.

关键词： Phase locked loops

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A cost-efficient 12-bit 20Msamples/s pipelined ADC

A cost-efficient 12-bit 20Msamples/s pipelined ADC

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Junmin, Cao Zhongjian, Chen Wengao, Lu Baoying, Zhao Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um CMOS technology, the ADC dissipates 65mw from a 5V supply, and achieves a peak SNDR of 70.1dB with a 1MHz full-scale sine input at 20MS/s. ©2008 IEEE.

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A novel calibration technique applying to an adaptive-bandwidth PLL

A novel calibration technique applying to an adaptive-bandwi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Song Ying Wang Yuan Jia Song Zhao Baoying Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781424421855

This paper proposes a novel calibration technique and its application on an adaptive-bandwidth *** new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference *** maximum calibration time is less than five comparison *** the calibration technique and an adaptive bandwidth,the PLL can maintain optimal performance during the whole working *** proposed circuit has been implemented in 0.18um CMOS logic *** show that the calibration time is less than 1.2μs,and the total locking time is less than 3μ*** PLL has good jitter performance within its operating range from 860MHz to 2.1GHz.

关键词： PLL calibration low jitter

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A method to lower power in speed negotiation algorithm of fiber channel

A method to lower power in speed negotiation algorithm of fi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Jin, Jie Yu, Dun Shan Cui, Xiao Xin Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424421855

In this paper, we propose a simple but effective method to reduce the power in the design of the Speed Negotiation Algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area. © 2008 IEEE.

关键词： Clocks

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A low power high speed ROIC design for 10241024 IRFPA with novel readout stage

A low power high speed ROIC design for 10241024 IRFPA with n...

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2008 IEEE International Conference on Electron devices and Solid-State circuits, EDSSC

作者： Liu, Chang Lu, Wengao Chen, Zhongjian Bian, Haimei Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424425402

A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024x1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10M/s per channel, with the total power dissipation of 56mW © 2008 IEEE.

关键词： Low power electronics

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Design and test results of a front-end ASIC for radiation detectors

Design and test results of a front-end ASIC for radiation de...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Yacong, Zhang Zhongjian, Chen Wengao, Lu Lijiu, Ji Zhao Baoying Key Laboratory of Microelectronic Devices and Circuits Institute Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5um CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900e. The power dissipation without the output buffer is about 2.6mW. © 2008 IEEE.

关键词： Application specific integrated circuits

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A 900MHz UHF RFID reader transceiver in 0.18m CMOS technology

A 900MHz UHF RFID reader transceiver in 0.18m CMOS technolog...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Ye, Le Liao, Huailin Song, Fei Chen, Jiang Xiao, Huilin Liu, Ruiqiang Liu, Junhua Wang, Xinan Wang, Yangyuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

This paper presents a UHF band (840MHz-925MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18m CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the transceiver. A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise corner. The transceiver, with an on-chip Power-amplifier (PA) driver to drive off-chip PA, supports DSB-ASK, SSB-ASK and PR-ASK modulation schemes. A sigma-delta PLL is also implemented for 250kHz channel hopping. Measurement results are given. Mixer achieves -8dBm PldB and 6.25dB noise figure, phase noise of PLL is -127dBc/Hz @ 1MHz offset and settling time of channel hopping is within 30s. Settling time of killing leakage is less than 15 μs. The sensitivity of receiver can be -81dBm @ 40 kHz link frequency (LF). The total silicon area of the transceiver is 13mm2, and draws 75mA for 1.8V supply voltage. © 2008 IEEE.

关键词： Transceivers

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