The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configuration...
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The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configurations of gate stack are simulated and *** is shown that the structure of double-layer buffer can improve the device performance *** important issues for FeFET scaling down are also discussed in this paper.
A low power Read-Out Integrated Circuit(ROIC) for a short-wave Infra-Red Focal Plane Array(IRFPA) is designed as a prototype for 1024×1024 image *** integration and readout scheme as well as highly efficient powe...
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A low power Read-Out Integrated Circuit(ROIC) for a short-wave Infra-Red Focal Plane Array(IRFPA) is designed as a prototype for 1024×1024 image *** integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme,novel low input capacitance column amplifier is *** Data rate is about 10M/s per channel,with a total power dissipation of 56mW.
＜正＞An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented.A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. the DN...
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＜正＞An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented.A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. the DNL/INL is 0.3/0.2LSB according to MATLAB simulation *** ADC is implemented in 0.5um CMOS technology and the total power dissipation is merely 96mW at a sampling rate of 200MHz.
The resistive switching behavior of Ag/SiN/Pt device was observed and studied for the first time. Resistance ratio larger than 410～2 and 10～4s retention time were achieved which indicating its potential for resistiv...
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The resistive switching behavior of Ag/SiN/Pt device was observed and studied for the first time. Resistance ratio larger than 410～2 and 10～4s retention time were achieved which indicating its potential for resistive switching memory application.A physical model is proposed to explain the resistive switching behaviors of Ag/SiN/Pt devices.
To improve the performances of ohmic contacts for GaN devices,a novel multilayer Ti/Al-based metal scheme (Ti/Al/Ti/ALTi/Al/Ti/Al/Ni/Au) on undoped AlGaN/GaN heterostructures was employed.A contact with pc(specific co...
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To improve the performances of ohmic contacts for GaN devices,a novel multilayer Ti/Al-based metal scheme (Ti/Al/Ti/ALTi/Al/Ti/Al/Ni/Au) on undoped AlGaN/GaN heterostructures was employed.A contact with pc(specific contact resistance) of 8.74E-07Ω·cm2,Re of 0.22Ω·mm was *** contacts with the novel metal structure were measured with I-V,SEM,HRTEM to show their *** results showed that ohmic contacts with novel structures have better surface morphology and proposed thermal stability than those using conventional Ti/Al/Ni/Au metal scheme,therefore ohmic contacts with novel structures should be better candidates for high power and high frequency GaN devices.
This paper implements a sixteen-order high-speed Finite Impose Response(TTR) filter with four different popular methods:Conventional multiplications and additions;Full custom Distributed Arithmetic(DA) scheme;Add-and-...
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This paper implements a sixteen-order high-speed Finite Impose Response(TTR) filter with four different popular methods:Conventional multiplications and additions;Full custom Distributed Arithmetic(DA) scheme;Add-and-Shift method with advanced calculation *** scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical *** of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed *** premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3%versus the largest conventional parallel multiplication implementation.
＜正＞An efficient encoding scheme is proposed for folding *** the encoder,XOR-OR encoding algoriflim and dynamic domino circuit are adopted.A novel method for wide-range error correction and bit synchronization is **...
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＜正＞An efficient encoding scheme is proposed for folding *** the encoder,XOR-OR encoding algoriflim and dynamic domino circuit are adopted.A novel method for wide-range error correction and bit synchronization is *** results show that the proposed encoder has several advantages:high speed,low power dissipation and small chip area.
This paper presents a UHF band（840MHz25MHz） RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC *** architecture and modules for the proposed transceiver are described and implemented i...
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This paper presents a UHF band（840MHz25MHz） RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC *** architecture and modules for the proposed transceiver are described and implemented in a standard 0.18μm CMOS process. To suppress the leakage signal from transmitter to receiver,directional coupler and leakage cancellation circuit are introduced in the transceiver.A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise *** transceiver,with an on-chip Power-amplifier（PA） driver to drive off-chip PA,supports DSB-ASK,SSB-ASK and PR-ASK modulation schemes.A sigma-delta PLL is also implemented for 250kHz channel *** results are *** achieves -8dBm P1dB and 6.25dB noise figure,phase noise of PLL is -127dBc/Hz @1MHz offset and settling time of channel hopping is within 30μ*** time of killing leakage is less than 15μ*** sensitivity of receiver can be -81dBm@40 kHz link frequency（LF）.The total silicon area of the transceiver is 13mnr,and draws 75mA for 1.8V supply voltage.
A front-end ASIC for semiconductor radiation detectors is *** is composed of a Charge Sensitive Amplifier(CSA),a pulse shaper,and a Peak Detect and Hold(PDH) ***-resistor is used as source degeneration component to re...
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A front-end ASIC for semiconductor radiation detectors is *** is composed of a Charge Sensitive Amplifier(CSA),a pulse shaper,and a Peak Detect and Hold(PDH) ***-resistor is used as source degeneration component to reduce the noise of current source in the *** ASIC has been designed in a 0.5um CMOS DPTM technology and tested with Verigy *** gain(PDH excluded) is 78.5mV/fC and the Equivalent Noise Charge(ENC) with detector disconnected is *** power dissipation without the output buffer is about 2.6mW.
This paper proposes a novel histogram BIST scheme for ADC static *** a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input *** on this property,a space decomposition tech...
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This paper proposes a novel histogram BIST scheme for ADC static *** a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input *** on this property,a space decomposition technique is proposed to reduce the testing *** utilizing this technique,ADC's static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.
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