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A Simple Nano-Scale Patterning Technology for FinFET Fabrication

A Simple Nano-Scale Patterning Technology for FinFET Fabrica...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Xu Han Chengen Yang Dingyu Li Shengdong Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper,a simple low-cost sub-50 nm silicon fin patterning technology is proposed and experimentally *** technology is based on a micro-meter level lithography equipment,that is,it does not need any critical photolithographic *** masking layer for fin formation is the nitride caped oxide layer which is reduced in width from sub-micrometer scale to nano-meter scale through a lateral etching in *** etching rate is shown to slow down as the etching process goes on.A nano-scale oxide hard mask can be achieved after the nitride is *** the cross-sectional view and top view of the etching process are shown by SEM *** indicate the simple patterning way is of low cost and under good control,and applicable to FinFET technology.

关键词： FinFET A Simple Nano-Scale Patterning Technology for FinFET Fabrication

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Optimization of explicit-pulsed flip-flops for high performance

Optimization of explicit-pulsed flip-flops for high performa...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Xiaoyang Zhang Song Jia Yuan Wang Ganggang Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Two novel structures for explicit-pulsed flip-flops are proposed in this *** charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures,and the short circuit power consumption is diminished by overcoming the race problem as *** results also indicate the new structures are ideal for high-speed and low-power digital design.

关键词： Optimization of explicit-pulsed flip-flops for high performance DCO EXW

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A CMOS TDI Readout Circuit for Infrared Focal Plane Array

A CMOS TDI Readout Circuit for Infrared Focal Plane Array

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Zhongjian Chen Wengao Lu Ju Tang Yacong Zhang Cao Junmin Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

A new structure 288x4 CMOS time delay and integration(TDI) readout integrated circuit(ROIC) is presented in this *** TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact *** experimental chip has been designed and fabricated in 0.5μm double-poly-three-metal CMOS ***-directional TDI,defective element deselection and two-gain option(1.015pC/2.03pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform *** readout speed of each out can reach 5MHz and the dynamic range is 75.6dB.

关键词： TDI A CMOS TDI Readout Circuit for Infrared Focal Plane Array

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A New Configuration Scheme for Delay Test in Non-simple LUT FPGA Designs

A New Configuration Scheme for Delay Test in Non-simple LUT ...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Botao Sun Jianhua Feng Teng Lin Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

With the increased use of FPGA in widespread applications,its' size and speed has been rapidly increased,so more and more problems associated with performance defects are *** defects such as delay defects will not lead to a functional fault, but will limit the frequency of the *** Stuck-at testing has not been sufficient to guarantee the reliability and quality,so testing delay fault becomes *** this paper,in order to improve the efficiency and coverage of delay test,we first select the most suitable delay fault model for FPGAs,which is a good simulation for the actual *** the same time we proposed a new configuration on the basis of *** method takes full advantage of the FPGAs' reconfiguration *** not only omits complex test pattern generation,but also optimizes the BIST circuits to minimize the area cost, and reaches higher fault *** verify the theory, we use Xilinx vertex4 devices on the experimental test, and achieved approving results.

关键词： FPGA configuration delay-test LUT MUX

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Impact Factors on the Performance of Schottky Barrier MOSFETs with Asymmetric Barrier Height at Source/Drain

Impact Factors on the Performance of Schottky Barrier MOSFET...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Du Xiong-Xiong Sun Lei Liu Xiao-Yan Han Ru-Qi Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/drain (A-SBFET) was numerically *** impact factors on the performance are *** results suggest the on-state characteristics of the devices are mainly determined by the source-side barrier height (SBH).Increasing SBH or decreasing body thickness can optimize the sub-threshold slope,and decreasing SBH can enhance the on-state current.

关键词： Impact Factors on the Performance of Schottky Barrier MOSFETs with Asymmetric Barrier Height at Source/Drain

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Fabrication and Characteristics of ZnO-based Thin Film Transistors

Fabrication and Characteristics of ZnO-based Thin Film Trans...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Dedong Han Yi Wang Shengdong Zhang Lei Sun Jinfeng Kang Xiaoyan Liu Gang Du Lifeng Liu Ruqi Han Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ZnO-based thin-film transistors(TFT) have been fabricated on p-Si(100) substrates by radio frequency(rf) magnetron sputtering at room temperature with a bottom gate *** XRD and SEM show that ZnO films had high crystalline *** ZnO films present an average optical transmission(including the glass substrate) of 80%in the visible part of the spectrum. The electrical properties of ZnO-based TFTs were investigated by I-V and I-V *** ZnO TFT operates in the enhancement mode with a channel mobility of 6.86 cm/V ? *** combination of transparency,high channel mobility and room temperature processing makes the ZnO-TFT a very promising low cost optoelectronic device for the next generation of flat panel display(FDP).

关键词： [IEEE keyword]Temperature measurement Sputtering X-ray scattering Films Substrates Thin film transistors Zinc oxide

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Efficient encoding scheme for folding ADC

Efficient encoding scheme for folding ADC

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.

关键词： Encoding Error correction Power dissipation Voltage microelectronics Circuit simulation Logic circuits Read only memory Binary codes Timing

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A Method to Lower Power in Speed Negotiation Algorithm of Fiber Channel

A Method to Lower Power in Speed Negotiation Algorithm of Fi...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Jie Jin Dun Shan Yu Xiao Xin Cui Key Laboratory of Microelectronic Devices and Circuits.Institute of Microelectronics Peking University

In this paper,we propose a simple but effective method to reduce the power in the design of the Speed Negotiation Algorithrn(SNA).Based on thoroughly analyzing the algorithm and the results of simulation,we identify the large timers,the most commonly used in the SNA,as the most power consuming *** paper further develops a partition algorithm to tackle the power issue of the large *** the proposed method, we can reduce the power by 30%as opposed to only 19%if directly applying clock-gating methodology. Combined with clock-gating methodology,we can get 38%reduction in power with no more than 5%increase in area.

关键词： A Method to Lower Power in Speed Negotiation Algorithm of Fiber Channel

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Optimization of explicit-pulsed flip-flops for high performance

Optimization of explicit-pulsed flip-flops for high performa...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Xiaoyang Zhang Song Jia Yuan Wang Ganggang Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

Two novel structures for explicit-pulsed flip-flops are proposed in this paper. The charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. Simulation results also indicate the new structures are ideal for high-speed and low-power digital design.

关键词： Flip-flops Clocks Latches Switches Energy consumption Circuit stability Sampling methods Pulse generation Master-slave microelectronics

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A CMOS TDI readout circuit for infrared focal plane array

A CMOS TDI readout circuit for infrared focal plane array

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Zhongjian Chen Wengao Lu Ju Tang Yacong Zhang Cao Junmin Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A new structure 288 × 4 CMOS time delay and integration (TDI) readout integrated circuit (ROIC) is presented in this paper. The TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact layout. An experimental chip has been designed and fabricated in 0.5 ¿m double-poly-three-metal CMOS technology. Bi-directional TDI, defective element deselection and two-gain option (1.015 pC/2.03 pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform IRFPA. The readout speed of each out can reach 5 MHz and the dynamic range is 75.6 dB.

关键词： Circuit testing Bidirectional control Detectors microelectronics Delay effects CMOS technology Systolic arrays Switches Timing Signal detection

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