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Microscopic mechanism of imprint in hafnium oxide-based ferroelectrics

Nano Research 2022年第4期15卷 3667-3674页

作者： Peng Yuan Ge-Qi Mao Yan Cheng Kan-Hao Xue Yunzhe Zheng Yang Yang Pengfei Jiang Yannan Xu Yuan Wang Yuhao Wang Yaxin Ding Yuting Chen Zhiwei Dang Lu Tai Tiancheng Gong Qing Luo Xiangshui Miao Qi Liu Key Laboratory of Microelectronic Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesNo.3Beitucheng West RoadBeijing 100029China University of Chinese Academy of Sciences 19 Yuquan RoadBeijing 100049China School of Integrated Circuits School of Optical and Electronic InformationHuazhong University of Science and Technology1037 Luoyu RoadWuhan 430074China Key Laboratory of Polar Materials and Devices(MOE) Department of ElectronicsEast China Normal University100 Guilin RoadShanghai 430079China Department of Mathematics and Theories Peng Cheng LaboratoryNo.2Xingke 1st StreetShenzhen 518055China

Hafnia-based ferroelectrics have greatly revived the field of ferroelectric memory(FeRAM),but certain reliability issues must be satisfactorily resolved before they can be widely applied in commercial *** particular,the imprint phenomenon severely jeopardizes the read-out reliability in hafnia-based ferroelectric capacitors,but its origin remains unclear,which hinders the development of its recovery *** this work,we have systematically investigated the imprint mechanism in TiN/Hf_(0.5)Zr_(0.5)O_(2)(HZO)/TiN ferroelectric capacitors using experiments and first-principles *** is shown that carrier injection-induced charged oxygen vacancies are at the heart of imprint in HZO,where other mechanisms such as domain pinning and dead layer are less *** imprint model based on electron de-trapping from oxygen vacancy sites has been proposed that can satisfactorily explain several experimental facts such as the strong asymmetric imprint,leakage current variation,and so *** on this model,an effective imprint recovery method has been proposed,which utilizes unipolar rather than bipolar voltage *** remarkable recovery performances demonstrate the prospect of improved device reliability in hafnia-based FeRAM devices.

关键词： hafnia-based ferroelectric imprint build-in electric field oxygen vacancy recovery

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Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors

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Science China(Information Sciences) 2020年第10期63卷 288-290页

作者： Xiaoqiao DONG Ming LI Wanrong ZHANG Yuancheng YANG Gong CHEN Shuang SUN Jianing WANG Xiaoyan XU Xia AN Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Faculty of Information Technology Beijing University of Technology

Dear editor,With the development of VLSI technology,gateall-around (GAA) silicon nano wire transistor(SNWT) has emerged as one of the most potential candidates for ultimately scaled CMOS devices at the end of the technology *** pioneering research studies have demonstrated super scalability and high performance with GAA SNWT [1-3].Whereas,in the practical fabrica-

关键词： gate-all-around nanowire effective gate length effective model asymmetrical

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Ferroelectric materials, devices, and chips technologies for advanced computing and memory applications: development and challenges

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Science China(Information Sciences) 2025年第6期 118-173页

作者： Xiao YU Ni ZHONG Yan CHENG Tianjiao XIN Qing LUO Tiancheng GONG Jiezhi CHEN Jixuan WU Ran CHENG Zhiyuan FU Kechao TANG Jin LUO Tianling REN Fei XUE Lin CHEN Tianyu WANG Xueqing LI Xiuyan LI Ping WANG Xinqiang WANG Jie SUN Anquan JIANG Peiyuan DU Bing CHEN Chengji JIN Jiajia CHEN Haoji QIAN Wei MAO Siying ZHENG Huan LIU Haiwen XU Can LIU Zhihao SHEN Xiaoxi LI Bochang LI Zheng-Dong LUO Jiuren ZHOU Yan LIU Yue HAO Genquan HAN Hangzhou Institute of Technology Xidian University Faculty of Integrated Circuits Xidian University Key Laboratory of Polar Materials and Devices(MOE) Department of Electronics East China Normal University State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of Sciences School of Information Science and Engineering Shandong University College of Integrated Circuit Zhejiang University School of Integrated Circuits Southeast University School of Integrated Circuits Peking University School of Integrated Circuits Tsinghua University Center for Quantum Matter School of Physics Zhejiang University School of Microelectronics State Key Laboratory of Integrated Chips and Systems Fudan University Department of Electronic Engineering Tsinghua University National Key Laboratory of Micro and Nano Fabrication Technology and the Department of Micro-Nano Electronics Shanghai Jiao Tong University State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-Optoelectronics School of Physics Peking University Hangzhou Huarui Chip Innovation Technology Co. Ltd.

Hafnium（Hf） oxide-based ferroelectric materials have emerged as a transformative platform for next-generation non-volatile memory and advanced computing technologies. This review comprehensively examines the development, challenges, and applications of HfO2ferroelectrics, emphasizing their CMOS compatibility, scalability, and robust polarization at nanoscale dimensions. Breakthroughs in doping strategies, stress engineering, and VO control have stabilized the metastable orthorhombic phase, enabling high-performance devices such as ferroelectric RAM（FeRAM）, ferroelectric field-effect transistors（FeFETs）, and ferroelectric tunnel junctions（FTJs）. These devices offer ultrafast switching, low power consumption, and multi-level storage, driving innovations in neuromorphic computing, in-memory processing, and cryogenic systems; nonetheless, they face ongoing challenges in reliability, such as fatigue and imprint effects, and scalability at sub-5 nm technology nodes. Emerging frontiers, such as wurtzite-structured nitrides（e.g., AlScN） and antiferroelectric ZrO2-based systems, have garnered significant attention due to their exceptionally high remanent polarization and promising potential for enhanced endurance, respectively. Further addressing the reliability issues of these emerging ferroelectric materials and the challenges associated with large-scale integration processes through interdisciplinary efforts will unlock the full potential of ferroelectric technologies, positioning them as pivotal enablers of post-Moore computing architectures and sustainable AI-driven applications.

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A novel tunnel FET design through hybrid modulation with optimized subthreshold characteristics and high drive capability

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Science China(Information Sciences) 2020年第2期63卷 245-247页

作者： Yang ZHAO Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University National Key Laboratory of Science and Technology on Micro/Nano Fabrication Peking University

Dear editor,As CMOS technology scaling down, the reduction of supply voltage and power consumption becomes extremely difficult due to the subthreshold swing(SS) limitation (60 m V/dec) at room *** FET (TFET) with band-to-band tunneling (BTBT) mechanism is regarded as one of the most promising emerging low-power devices due to its sub-60 m V/dec SS and ultra-low off-current

关键词： A novel tunnel FET design through hybrid modulation with optimized subthreshold characteristics and high drive capability FET

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A High Dynamic Range Pixel Circuit with High-voltage Protection for 128×128 Linear-mode APD Array 15

A High Dynamic Range Pixel Circuit with High-voltage Protect...

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15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

作者： Gu, Yuting Lu, Wengao Niu, Yuze Zhang, Yacong Chen, Zhongjian Key Laboratory of Microelectronic Devices and Circuits Peking University Department of Microelectronics China

ISBN: (纸本)9781728162355

This paper presents a high dynamic range pixel circuit with high-voltage protection for 128×128 Linear-mode avalanche photodiode (LM-APD) array. The pixel circuit includes a high-voltage transistor, a pixel-level analog-to-digital converter (ADC), and a high-voltage protection circuit based on circuit-shared. Through circuit-shared, the pixel-level A/D conversion and high-voltage protection are completed efficiently. Meanwhile, the dynamic range of the entire circuit is greatly improved. The chip is designed in 0.18µm CMOS process. The frame rate is 100Hz and the resolution is 16bit. The simulation results indicate that the dynamic range is 94dB and the power consumption is 5µW per pixel. The pixel pitch is 100µm, which can be reduced further with smaller APD detector. © 2020 IEEE.

关键词： Surge protection

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Back Gate Controlled Pseudo-P-Channel GaN HFET

Back Gate Controlled Pseudo-P-Channel GaN HFET

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Semiconductor and Electronic Technology (ISSET), International Symposium on

作者： Li Guan Qi Li Lanyi Liang Lei Wang Xin Zhang Haiou Li Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic Technology Guilin China Department of Guangxi Zhuang Autonomous Region Key Laboratory of Microelectronic Devices and Integrated Circuits Education Guilin China

ISBN: (数字)9798350390285

ISBN: (纸本)9798350390292

This paper proposes a novel pseudo-p-channel AlGaN/GaN heterostructure field-effect transistor (PP-HFET). As semiconductor technology advances, GaN devices are preferred for high-power and high-frequency applications due to their high electron mobility, breakdown field, and wide bandgap. Traditional AlGaN/GaN HFETs perform well because of their high electron density and mobility in the 2DEG channel. However, conventional n-type AlGaN/GaN HFETs are limited in applications requiring p-channel devices. The PP-HFET consists of a top reference electrode and a back-gate control electrode. During operation, the top reference electrode of the PP-HET is biased negatively, rendering the device to be initially in the off state. When a negative voltage is applied to the back gate, the two-dimensional electron gas (2DEG) in the channel is regenerated owing to the compensation effect of the electric field. The more negative the back-gate voltage, the higher the ON current of the device, exhibiting the same characteristics as those of a p-channel device. The effects of the device parameters on the output and transfer characteristics are comprehensively examined, and an analytical model is presented. The simulation results illustrate that the threshold voltage of the proposed device based on the back-gate control is approximately -3.5 V, and the current density is as high as 0.1 A/mm, which is much higher than that of the conventional E-mode p-channel GaN HFET based on two-dimensional hole gas.

关键词： Electrodes Manufacturing processes Simulation HEMTs Logic gates Threshold voltage Wide band gap semiconductors MODFETs Integrated circuit reliability Aluminum gallium nitride

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A Depletion-enhanced N Layers Stacked LDMOS

A Depletion-enhanced N Layers Stacked LDMOS

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Semiconductor and Electronic Technology (ISSET), International Symposium on

作者： Qi Li Lanyi Liang Li Guan Tianbao Dang Hong Huang Yonghe Chen Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic Technology Guilin China Navigation Department of Guangxi Zhuang Autonomous Region Key Laboratory of Microelectronic Devices and Integrated Circuits Guilin China

ISBN: (数字)9798350390285

ISBN: (纸本)9798350390292

With the development of power integrated circuits, LDMOS devices assume a significant role in power device applications due to their elevated input impedance and enhanced conversion rate. Nonetheless, a contradictory relationship exists between the breakdown voltage and specific on-resistance in power LDMOS devices. Consequently, an n-layer stacked lateral double-diffused metal-oxide-semi conductor transistor(SLDMOS) is proposed, in which numerous MOS cells are stacked under the same chip area. The on-state resistance $(\mathrm{R}_{\mathrm{o}\mathrm{n}})$ of the n layers S-LDMOS is decreased significantly because of the vertical parallel connection, also the interference among devices is weakened through electrode interconnection isolated by oxidation layer. Multiple drift regions are formed by alternate epitaxy N-layer (drift region) and P-layer (substrate), and each drift region is depleted by the top and bottom P substrates, leading to a much lower $\mathrm{R}_{\mathrm{o}\mathrm{n}}$ . The lightly-doped substrate and N/P top region are used to improve the breakdown characteristics, and the floating P layers are introduced to enhance the depletion effect in drift regions and decrease device thicknesses. By optimizing the configuration, a balanced trade-off is obtained. The simulation results indicate that compared with the traditional LDMOS, the 2 layers S-LDMOS exhibits a BV of 356 V and a specific on resistance $(\mathrm{R}_{\mathrm{o}\mathrm{n},\mathrm{s}\mathrm{p}})$ of 13.56 $\boldsymbol{\mathrm{m}\Omega\cdot \text{cm}^devices,}$ an improvement of 26.2 % and 71.6%, respectively. And the $\mathrm{R}_{\mathrm{o}\mathrm{n}}$ , sp of n layers S-LDMOS will be reduced to less than 1/n of C-LDMOS further.

关键词： Resistance Simulation Stacking Interference Oxidation Epitaxial growth Power integrated circuits Substrates Optimization Testing

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On-Chip Incremental Learning based on Unsupervised STDP Implementation

On-Chip Incremental Learning based on Unsupervised STDP Impl...

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IEEE International Conference on Artificial Intelligence circuits and Systems (AICAS)

作者： Guang Chen Jian Cao Shuo Feng Zilin Wang Yi Zhong Qibin Li Xiongbo Zhao Xing Zhang Yuan Wang School of Software and Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center Peking University Beijing China School of Integrated Circuits Peking University Beijing China Beijing Aerospace Automatic Control Institute Beijing China

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Spiking neural network (SNN), a bio-inspired neuron network, utilizes a learning rule named spike-timing-dependent plasticity (STDP) to achieve high-performance unsupervised learning. However, it may suffer from catastrophic forgetting when the distribution of new data significantly differs from that of old data. To address this issue, an incremental learning implementation for ship classification is presented in this paper. We develop an incremental learning algorithm based on STDP and corresponding platform. A competitive SNN is built into our algorithm, and add-STDP is utilized to update the weights of network for efficient learning. To enhance learning performance, we incorporate weight decay. And to avoid catastrophic forgetting, we incorporate data replay. The corresponding learning platform consists of the FPGA Zynq 7100 and the STDP neuromorphic prototype chip, and our algorithm is executed on the chip. We evaluate the ship classification task on our platform, which demonstrates the superior potential of our on-chip implementation for incremental learning.

关键词： Incremental learning Neuromorphics Neurons Prototypes Spiking neural networks Classification algorithms System-on-chip

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Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction

Experimental Demonstration of A CT-FeFET Array with Intrinsi...

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International Electron devices Meeting (IEDM)

作者： Chao Li Jie Yu Xumeng Zhang Zhaohao Zhang Fangduo Zhu Siyuan Ouyang Pei Chen Lingli Cheng Gaobo Xu Qingzhu Zhang Huaxiang Yin Qi Liu Ming Liu State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000x and 4x improvements than GPU in power consumption and memory overhead.

关键词： Performance evaluation Power demand Neuromorphics Memory management Graphics processing units Trajectory Vehicle dynamics Synapses Long short term memory FeFETs

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Low power and high uniformity of HfOx-based RRAM via tip-enhanced electric fields

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Science China(Information Sciences) 2019年第10期62卷 164-170页

作者： Xiaokang LI Baotong ZHANG Bowen WANG Xiaoyan XU Yuancheng YANG Shuang SUN Qifeng CAI Shijie HU Xia AN Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

In this paper, the HfOx-based resistive random access memory（RRAM） devices with sub-100 nm pyramid-type electrodes were fabricated. With the help of tip-enhanced electric field around the pyramid-type electrodes, it was experimentally demonstrated that the novel devices have better cycle-to-cycle variation control, lower forming/set voltage（1.97/0.7V） and faster switching speed（≤30 ns under 0.9V pulse） as well as better endurance reliability than conventional flat electrode resistive memory devices. In addition,the novel RRAM is experimentally demonstrated with independence of electrode number for the first time to present great potential in scaling down. This novel structure metal-oxide based RRAM will be suitable for the future low-power non-volatile memory application.

关键词： RRAM pyramid-type electrode variation reliability switching speed conducting filament

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