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On the effect of scattering in Schottky Barrier MOSFETs

On the effect of scattering in Schottky Barrier MOSFETs

引用

IEEE Conference on Electron devices and Solid-State circuits

作者： Lang Zeng Xiao Yan Liu Gang Du Jin Feng Kang Ru Qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

In this paper, we performed a simulation on a 45-nm UTB SOI Schottky Barrier MOSFETs using our two dimensional Ensemble full band Monte Carlo simulator to evaluate the effect of scattering in Schottky Barrier MOSFETs (SB FETs). The carrier transport details for both ballistic case and scattering case are simulated and analyzed. The scattering plays a less important role on the performance in SB FETs than in conventional highly doped S/D MOSFETs. Based on our analysis, the inappropriate of Natoripsilas ballistic transport model applied to SB FETs is revealed and the reason is due to the existence of non-local tunneling. Further development of the quasi ballistic model is necessary to include this non-local effect.

关键词： Schottky barriers MOSFETs FETs Optical scattering Acoustic scattering Ballistic transport Monte Carlo methods Electromagnetic compatibility microelectronics Performance evaluation

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An acquisition circuit in Global Positioning System receivers

An acquisition circuit in Global Positioning System receiver...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Xiaoxin Cui Chungan Peng Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855;9781424421862

The conventional matched filter structures are investigated in this paper. An acquisition circuit based on the polyphase form matched filter in Global Positioning System (GPS) receiver is provided. At the cost of less hardware resource, the significant advantage in the speed of synchronization is offered. For 32×128 polyphase form matched filter, the critical path delay approximately reduces 1/2, the sample frequency would be double.

关键词： circuits Global Positioning System Frequency synchronization Matched filters Signal generators Hardware Shift registers Delay Satellites Glands

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Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN heterostructures

Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN het...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Zhihua Dong Jinyan Wang Min Yu Yilong Hao C. P. Wen Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

To improve the performances of ohmic contacts for GaN devices, a novel multilayer Ti/Al-based metal scheme (Ti/Al/Ti/Al/Ti/Al/Ti/Al/Ni/Au) on undoped AlGaN/GaN heterostructures was employed. A contact with ¿c (specific contact resistance) of 8.74E-07 ¿·cm2, Rc of 0.22 ¿·mm was demonstrated. Ohmic contacts with the novel metal structure were measured with I-V, SEM, HRTEM to show their properties. The results showed that ohmic contacts with novel structures have better surface morphology and proposed thermal stability than those using conventional Ti/Al/Ni/Au metal scheme, therefore ohmic contacts with novel structures should be better candidates for high power and high frequency GaN devices.

关键词： Ohmic contacts Aluminum gallium nitride Gallium nitride Gold Nonhomogeneous media Contact resistance Electrical resistance measurement Surface morphology Surface resistance Thermal stability

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A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technology

A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technol...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Le Ye Huailin Liao Fei Song Jiang Chen Huilin Xiao Ruiqiang Liu Junhua Liu Xinan Wang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper presents a UHF band (840 MHz~925 MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18 μm CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the transceiver. A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise corner. The transceiver, with an on-chip power-amplifier (PA) driver to drive off-chip PA, supports DSB-ASK, SSB-ASK and PR-ASK modulation schemes. A sigma-delta PLL is also implemented for 250 kHz channel hopping. Measurement results are given. Mixer achieves -8dBm P1 dB and 6.25 dB noise figure, phase noise of PLL is -127 dBc/Hz @ 1 MHz offset and settling time of channel hopping is within 30 μs. Settling time of killing leakage is less than 15 μs. The sensitivity of receiver can be -81dBm @ 40 kHz link frequency (LF). The total silicon area of the transceiver is 13 mm 2 , and draws 75 mA for 1.8 V supply voltage.

关键词： CMOS technology Radiofrequency identification Transceivers Phase locked loops Protocols ISO standards IEC standards CMOS process Transmitters Directional couplers

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Low power Folding/Interpolating ADC with a novel dynamic encoder based on ROM theory

Low power Folding/Interpolating ADC with a novel dynamic enc...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Jilei Yin Yuan Wang Song Jia Zhen Liu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35 um digital CMOS process, the whole ADC consumes only 35 mW at a 3.3 V voltage supply.

关键词： Read only memory Voltage Logic circuits Power dissipation Logic arrays microelectronics Analog-digital conversion Signal generators Binary codes Tail

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A low power ROIC design for 1024×1024 IRFPA 9th

A low power ROIC design for 1024×1024 IRFPA

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Chang Liu Wengao Lu Zhongjian Chen Jing Li Yacong Zhang Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A low power Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024×1024 image system. Ripple integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme, novel low input capacitance column amplifier is proposed. The Data rate is about 10 M/s per channel, with a total power dissipation of 56 mW.

关键词： Power dissipation Capacitors Switches Linearity Detectors microelectronics Prototypes Parasitic capacitance MOSFET circuits Cooling

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The implementation methods of high speed FIR filter on FPGA

The implementation methods of high speed FIR filter on FPGA

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Ying Li Chungan Peng Dunshan Yu Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.

关键词： Finite impulse response filter Field programmable gate arrays Arithmetic Job shop scheduling Digital signal processing microelectronics Energy consumption Programmable logic arrays Circuit synthesis Table lookup

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CMOS folding and interpolating ADC with a mixed-averaging distributed T/H circuit

CMOS folding and interpolating ADC with a mixed-averaging di...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.

关键词： Sampling methods Power dissipation Switches Circuit simulation CMOS technology Synchronization Interpolation Clocks CMOS analog integrated circuits microelectronics

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A novel linear histogram BIST for ADC

A novel linear histogram BIST for ADC

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Jianguo Ren Jianhua Feng Hongfei Ye Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property, a space decomposition technique is proposed to reduce the testing time. By utilizing this technique, ADC¿s static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.

关键词： Histograms Built-in self-test Hardware microelectronics Laboratories Circuit testing Analytical models Parameter estimation Computational modeling Circuit faults

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A comprehensive study on Schottky barrier nanowire transistors (SB-NWTs): Principle, physical limits and parameter fluctuations

A comprehensive study on Schottky barrier nanowire transisto...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Liangliang Zhang Zhaoyi Kang Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855;9781424421862

P-type Schottky barrier nanowire transistors (p-SB-NWTs) are computational studied in this paper. We analyzed the working principle and physical limits on their performance in details. The impact of Schottky contact of SB-NWTs on the current drivability, gate control and RF performance are studied comparing with conventional silicon nanowire transistors (SNWTs). It is pointed out that the inferior performance of SB-NWTs can not be solved by changing the S/D or channel materials. On the other hand, small V t , F t and on-off ratio fluctuation caused by process variation on channel diameter are observed, which is an advantage of SB-NWTs.

关键词： Schottky barriers Fluctuations MOSFETs Silicon Tunneling Silicides Nanoscale devices microelectronics CMOS technology Contact resistance

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