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Switching at Less Than 60 mV/Decade with a “Cold” Metal as the Injection Source

Physical Review Applied 2020年第6期13卷 064037-064037页

作者： Fei Liu Institute of Microelectronics and Key Laboratory of Microelectronics Devices and Circuits (MoE) Peking University Beijing 100871 China

Power dissipation is a great challenge for the continuous scaling down and performance improvement of CMOS technology, due to the thermionic-current switching limit of conventional MOSFETs. In this paper, we show that this problem can be overcome by using a “cold” metal as the injection source of a transistor; these metals are different from conventional metals and can filter out high-energy electrons to break the “Boltzmann tyranny.” It is proved that the subthreshold swing of the thermionic current of a transistor using a “cold”-metal contact can be much smaller than 60 mV/decade at room temperature. Specifically, the two-dimensional transition-metal-dichalcogenide (TMD) “cold” metals NbX2 and TaX2 (X=S,Se,Te) are proposed as injection sources for FETs. Quantum transport simulations indicate that a promising switching efficiency and on-state current can be achieved using TMD “cold”-metal injection sources, which is beneficial for energy efficiency.

关键词： Ballistic transport Band gap Thermionic emission Field-effect transistors Metals Transition metal dichalcogenides First-principles calculations

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Low power and high uniformity of HfOx-based RRAM via tip-enhanced electric fields

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中国科学:化学（英文版） 2019年第10期62卷 160-166页

作者： Xiaokang LI Baotong ZHANG Bowen WANG Xiaoyan XU Yuancheng YANG Shuang SUN Qifeng CAI Shijie HU Xia AN Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking University Beijing 100871 China

In this paper,the HfOx-based resistive random access memory (RRAM) devices with sub-100 nm pyramid-type electrodes were *** the help of tip-enhanced electric field around the pyramid-type electrodes,it was experimentally demonstrated that the novel devices have better cycle-to-cycle variation control,lower forming/set voltage (1.97/0.7 V) and faster switching speed (≤ 30 ns under 0.9 V pulse) as well as better endurance reliability than conventional flat electrode resistive memory *** addition,the novel RRAM is experimentally demonstrated with independence of electrode number for the first time to present great potential in scaling *** novel structure metal-oxide based RRAM will be suitable for the future low-power non-volatile memory application.

关键词： RRAM pyramid-type electrode variation reliability switching speed conducting filament

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Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver

arXiv

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arXiv 2024年

作者： Chen, Hegan Yang, Jichang Chen, Jia Wang, Songqi Wang, Shaocong Wang, Dingchen Tian, Xinyu Yu, Yifei Chen, Xi Lin, Yinan He, Yangu Wu, Xiaoshan Li, Yi Zhang, Xinyuan Lin, Ning Xu, Meng Li, Yi Zhang, Xumeng Wang, Zhongrui Wang, Han Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

Digital twins, the cornerstone of Industry 4.0, replicate real-world entities through computer models, revolutionising fields such as manufacturing management and industrial automation. Recent advances in machine learning provide data-driven methods for developing digital twins using discrete-time data and finite-depth models on digital computers. However, this approach fails to capture the underlying continuous dynamics and struggles with modelling complex system behaviour. Additionally, the architecture of digital computers, with separate storage and processing units, necessitates frequent data transfers and Analogue-Digital (A/D) conversion, thereby significantly increasing both time and energy costs. Here, we introduce a memristive neural ordinary differential equation (ODE) solver for digital twins, which is capable of capturing continuous-time dynamics and facilitates the modelling of complex systems using an infinite-depth model. By integrating storage and computation within analogue memristor arrays, we circumvent the von Neumann bottleneck, thus enhancing both speed and energy efficiency. We experimentally validate our approach by developing a digital twin of the HP memristor, which accurately extrapolates its nonlinear dynamics, achieving a 4.2-fold projected speedup and a 41.4-fold projected decrease in energy consumption compared to state-of-the-art digital hardware, while maintaining an acceptable error margin. Additionally, we demonstrate scalability through experimentally grounded simulations of Lorenz96 dynamics, exhibiting projected performance improvements of 12.6-fold in speed and 189.7-fold in energy efficiency relative to traditional digital approaches. By harnessing the capabilities of fully analogue computing, our breakthrough accelerates the development of digital twins, offering an efficient and rapid solution to meet the demands of Industry 4.0. © 2024, CC BY-NC-SA.

关键词： Energy utilization

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Dilution-induced current-density increase in disordered organic semiconductor devices: A kinetic Monte Carlo study

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Physical Review Applied 2024年第1期21卷 014050-014050页

作者： Feiling Yang Harm van Eersel Jiawei Wang Quan Niu Peter A. Bobbert Reinder Coehoorn Feilong Liu Guofu Zhou Guangdong Provincial Key Laboratory of Optical Information Materials and Technology & Institute of Electronic Paper Displays South China Academy of Advanced Optoelectronics South China Normal University Guangzhou 510006 People’s Republic of China Department of Applied Physics and Institute for Complex Molecular Systems Eindhoven University of Technology Eindhoven University of Technology P.O. Box 513 Eindhoven Manitoba 5600 Netherlands Simbeyond B.V. Het Eeuwsel 57 Eindhoven AS 5612 Netherlands Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing 100029 China State Key Laboratory of Luminescent Materials and Devices South China University of Technology Guangzhou 510640 People’s Republic of China Shenzhen Guohua Optoelectronics Tech. Co. Ltd. Shenzhen 518110 People’s Republic of China

Using three-dimensional kinetic Monte Carlo simulations, we systematically investigate the effect of dilution with an inert material on the current density in unipolar sandwich-type disordered organic semiconductor devices. Such a dilution technique was studied experimentally by Abbaszadeh et al. [Nat. Mater. 15, 628 (2016)], who observed a dilution-induced increase of the current density. The authors explained the effect as a result of a reduced density of trapped charges (“trap dilution”), assuming an exponential density of trap states. Our simulations support this explanation, and show under which conditions this trap-dilution-induced increase of the current density becomes more than outweighed by the negative effect of the dilution-induced decrease of the mobility. The effect is studied for sets of systematically varied material parameters, including systems with a Gaussian shape of the host and trap DOS.

关键词： Carrier dynamics Energy transport Optoelectronics Surface & interfacial phenomena Disordered systems Organic LEDs Organic semiconductors Monte Carlo methods

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A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection

A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC w...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiaolong Chen Enbin Gong Hao Zhang Le Ye Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking university Beijing 100871 China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper proposed a pseudo-open boost DC-DC converter whose input voltage ranges from 300mV-to-500mV and output voltage ranges from 1.2V-to-1.8V. The output power ranges from 1μW to 158μW. Three key structures are designed to realize the high energy conversion efficiency when the load reaches ultra-light: the pseudo open-loop structure, the frequency-programmable oscillator, and the hybrid zero current detection (H-ZCD) circuit. The pseudo open-loop structure eliminates the analog comparators or error amplifiers used in converter and the quiescent power loss is much reduced. The frequency-programmable ring oscillator is able to output 9-bit binary frequency ranges from 500Hz-100KHz, so the power consumption of clock generation is saved when load power reaches to ultra-light. The proposed H-ZCD is designed to reduce the inductor power loss with just tiny power consumption. Accordingly, the high efficiency boost DC-DC works in the discontinuous condition mode (DCM) and the constant on time pulse frequency modulation (PFM) is proposed. As a simulation result, the peak efficiency of the converter reaches to 86.7% while the load power is 13.7μW.

关键词： Ring oscillators DC-DC power converters Power demand Switches Capacitors Energy efficiency

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An 81–99 GHz Tripler with Fundamental Cancellation and 3rd Harmonic Enhancement Technique in 40-nm CMOS

An 81–99 GHz Tripler with Fundamental Cancellation and 3rd ...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiaolei Su Xiucheng Hao Dong Wang Zhengkun Shen Zexue Liu Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

An 81–99 GHz tripler for wireless transceiver LO generation is presented in this paper. To suppress the fundamental signal and enhance the 3rd harmonic, the inversion signal is applied to the gate of the cascading transistor of the push-push differential pair. A capacitor is connected to the source and drain of the cascading transistor to further suppress the fundamental signal. Without additional filters, the tripler achieves more than 40 dBc of fundamental suppression with an even harmonic suppression of up to 60 dBc. The tripler reaches an output power of −2.6 dBm (4-dBm input) at 91.5 GHz with a 20% bandwidth of from 81 to 99 GHz. The core area of the chip occupies only 190 μm×530 μm in TSMC 40-nm CMOS process and consumes 28.2 mW.

关键词： Harmonic analysis Power harmonic filters Transistors Radio frequency Parasitic capacitance Capacitors Inductors

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Investigation of Vertically Stacked Horizontal Gate-All-Around SI Nanosheet Ion Sensitive Field Effect Transistor For Detection of C-Reactive Protein

Investigation of Vertically Stacked Horizontal Gate-All-Arou...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yang Liu Qingzhu Zhang Junjie Li Cinan Wu Lei Cao Yanna Luo Zhaohao Zhang Shuhua Wei Qianhui Wei Jiaxin Yao Jiawei Hu Meiyan Qin Enxu Liu Yanchu Han LianLian Li YingLu Li Tao Yang Na Zhou Jianfeng Gao Junfeng Li Key Laboratory of Microelectronic Devices and Integration Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China College of Big Data and Information Engineering Guizhou University Guiyang China School of Information Science and Technology North China University of Technology Beijing China State Key Laboratory of Advanced Materials for Smart Sensing GRINM Group Co. Ltd. Beijing China

In this work, based on advanced gate-all-around (GAA) technology, the extended sensing gate (ESG) GAA Si nanosheet (SiNS) ion sensitive field effect transistor (ISFET) sensor was fabricated and reported for the first time. Due to the GAA structures and the vertically-stacked SiNS channels, the average sensitivity of the ESG GAA SiNS ISFET sensor can be reached 58.8 mV/pH, which provides good gate control and ultra-sensitive detection capabilities. In addition, the actual minimum detection concentration of C-reactive protein (CRP) by ESG GAA SiNS ISFET sensor in 1$\times$ PBS environment is as low as 100pg/mL, which is much lower than the normal concentration of human body.

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Reversible and Irreversible Polarization Degradation of Hf0.5Zr0.5O2 Capacitors with Coherent Structural Transition at Elevated Temperatures

Reversible and Irreversible Polarization Degradation of Hf0....

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Annual International Symposium on Reliability Physics

作者： Zhaomeng Gao Tianjiao Xin Cheng Liu Yilin Xu Yiwei Wang Yunzhe Zheng Rui Wang Xiaotian Li Yonghui Zheng Kai Du Diqing Su Zhaohao Zhang Huaxiang Yin Weifeng Zhang Chao Li Xiaoling Lin Haitao Jiang Sannian Song Zhitang Song Yan Cheng Hangbing Lyu Key Laboratory of Polar Materials and Devices (MOE) East China Normal University Shanghai China Hualu Technologies Co. Shanghai China National Key Laboratory of Materials for Integrated Circuits Shanghai Institute of Microsystem and Information Technology (CAS) Shanghai China Huawei Technologies Co. Shenzhen China Institute of Microelectronics (CAS) Beijing China Key Laboratory of Photovoltaic Materials of Henan Province Henan University Kaifeng China China Electronic Product Reliability and Environmental Testing Research Institute Guangzhou China East China Normal University Lingang Research Institute Shanghai China

ISBN: (数字)9798350369762

ISBN: (纸本)9798350369779

In this study, we investigated the reversible and irreversible polarization degradation of hafnia-based ferroelectric capacitors (FeCAPs) using the state-of-the-art spherical aberration corrected transmission electron microscope (Cs-TEM) with realtime temperature changes. The key observations are as follows: (1) Rapid thermal annealing (RTA) results in incomplete formation of the orthorhombic (o-) phase in the ferroelectric (FE) material, leading to a coherent phase boundary (CPB) between o- and tetragonal (t-) structures. (2) The movement of the o-/t-CPB with temperature corresponds to reversible changes in polarization of hafnia-based FeCAPs. (3) Irreversible degradation in polarization occurs due to migration of the o-/monoclinic (m-) CPB with temperature. These findings provide a new perspective for evaluating the stability of the o-phase in fluorite-type FE materials and offer guidance for optimizing their properties through regulation strategies.

关键词： Degradation Temperature Transmission electron microscopy Microscopy Capacitors Iron Regulation

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A 160×120 ROIC with non-uniformity calibration for silicon diode uncooled IRFPA

A 160×120 ROIC with non-uniformity calibration for silicon ...

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2019 IEEE International Conference on Electron devices and Solid-State circuits, EDSSC 2019

作者： Zhu, Yajun Niu, Yuze Lu, Wengao Huang, Zhaofeng Zhang, Yacong Chen, Zhongjian Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics Peking University Beijing China

ISBN: (纸本)9781728102863

This paper presents a ROIC (Readout Integrated Circuit) with NUC (Non-uniformity Calibration), which is applied in a silicon diode uncooled IRFPA (Infrared Focal Plane Array). We propose blind pixel to calibrate chip temperature non-uniformity and DAC-based calibration for calibrating process non-uniformity. The ROIC is fabricated using a 0.35\mu \mathrm{m} CMOS process with array size of 160\times 120. Power consumption of the ROIC is 41mW, noise of the DAC is less than 2\muV, and the circuit's SNR (Signal-to-Noise Ratio) is 72dB. © 2019 IEEE.

关键词： Pixels

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Geometric Variability Aware Quantum Potential based Quasi-ballistic Compact Model for Stacked 6 nm-Thick Silicon Nanosheet GAA-FETs

Geometric Variability Aware Quantum Potential based Quasi-ba...

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International Electron devices Meeting (IEDM)

作者： Shijie Huang Zhenghua Wu Haoqing Xu Jingrui Guo Lihua Xu XinLv Duan Qian Chen Guanhua Yang Qingzhu Zhang Huaxiang Yin Lingfei Wang Ling Li Ming Liu Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Advanced Integrated Circuits R&D Center Institute of Microelectronic of the Chinese Academy of Sciences Beijing China

Quantum-corrected quasi-ballistic compact model is developed for Stacked Silicon Nanosheet (SiNS) Gate-all-around (GAA) FETs. Theories of Density-Gradient-Poisson (DG-P), Singular perturbation and quasi-ballistic to interpret quantum mechanicals on density profile and charge transport are employed in analytical expressions of current, terminal charge and trans-capacitance. Besides, the model incorporates ultra-scaling induced subthreshold degradation and is rigidly verified by comparing to 6-nm-thick-SiNS based experiments (of both ${P-}$ and $N$ -GAAFET) and GTS simulations (of down to 15 nm channel length). Instead of classical Schrodinger-Poisson theory, it holds features of computation-efficiency and SPICE-compatibility. Especially, awareness of geometric variability enables performance and reliability assessments that statistical effects of stacked nanosheets on on-state voltage are predicted. Hence, this high-efficient quantum corrected model is promising in designing integrated circuits and developing a geometry aware design-technology co-optimization flow in the next generation technology node.

关键词： Electric potential Simulation Field effect transistors Gallium arsenide Logic gates Mathematical models Silicon

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