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arXiv 2024年

作者： Yu, Yifei Wang, Shaocong Zhang, Woyu Zhang, Xinyuan Wu, Xiuzhe He, Yangu Yang, Jichang Zhang, Yue Lin, Ning Wang, Bo Chen, Xi Wang, Songqi Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Hong Kong Institute of Mind The University of Hong Kong Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong Hong Kong

Human beings construct perception of space by integrating sparse observations into massively interconnected synapses and neurons, offering a superior parallelism and efficiency. Replicating this capability in AI finds wide applications in medical imaging, AR/VR, and embodied AI, where input data is often sparse and computing resources are limited. However, traditional signal reconstruction methods on digital computers face both software and hardware challenges. On the software front, difficulties arise from storage inefficiencies in conventional explicit signal representation. Hardware obstacles include the von Neumann bottleneck, which limits data transfer between the CPU and memory, and the limitations of CMOS circuits in supporting parallel processing. We propose a systematic approach with software-hardware co-optimizations for signal reconstruction from sparse inputs. Software-wise, we employ neural field to implicitly represent signals via neural networks, which is further compressed using low-rank decomposition and structured pruning. Hardware-wise, we design a resistive memory-based computing-in-memory (CIM) platform, featuring a Gaussian Encoder (GE) and an MLP Processing Engine (PE). The GE harnesses the intrinsic stochasticity of resistive memory for efficient input encoding, while the PE achieves precise weight mapping through a Hardware-Aware Quantization (HAQ) circuit. We demonstrate the system’s efficacy on a 40nm 256Kb resistive memory-based in-memory computing macro, achieving 31.5×, 35.5×, and 47.2× energy efficiency improvements and 10.8×, 38.8×, and 6.2× parallelism improvements without compromising reconstruction quality in tasks like 3D CT sparse reconstruction, novel view synthesis, and novel view synthesis for dynamic scenes. This work advances the AI-driven signal restoration technology and paves the way for future efficient and robust medical AI and 3D vision applications. Copyright © 2024, The Authors. All rights reserved.

关键词： Signal reconstruction

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Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology

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Science China(Information Sciences) 2018年第10期61卷 285-287页

作者： Bingxin ZHANG Xia AN Pengqiang LIU Xiangyang HU Ming LI Xing ZHANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Ge has been considered as a very promising candidate as a channel material of MOSFET to extend Moore’s law beyond sub-7 nm node, due to its high and symmetric mobility, as well as the compatibility with conventional Si process [1, 2].In spite of higher carrier mobility than Si, there are still several challenges for Ge MOSFETs, such as low electrical concentration of n-type dopants and high electron Schottky barrier height, resulting in large source/drain (S/D) series resistance.

关键词： Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology NPP Ni

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Direct Cu-polyimide Bonding Achieved by Surface Activation and Pt-catalyzed Formic Acid Atmosphere

Direct Cu-polyimide Bonding Achieved by Surface Activation a...

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IEEE International Conference on Integrated circuits, Technologies and Applications (ICTA)

作者： Ying Meng Runhua Gao Xinhua Wang Xiaojuan Chen Sen Huang Ke Wei Dahai Wang Fengwen Mu Xinyu Liu High-Frequency High-Voltage Device and Integrated Circuits R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665417488

Recent flexible printed circuit applications of high-frequency wireless communication systems require thicker metal layers on substrates for lower ohmic losses. In this paper, a Cu layer over 50-micron thick was directly generated on the polyimide substrate by heterogeneous bonding method without interlayer. The polyimide was first sputtered a 200 nm-thick Cu layer, and then was activated by oxygen plasma to improve its hydrophilicity and achieve direct adhesion between polyimide and nanoscale Cu deposition, and eventually was bonded with a 50micron-thick Cu foil in a Pt-catalyzed formic acid atmosphere by thermo-compression. The effectiveness of this method was verified by comparing bonding interfaces, shear strength, and fracture modes of bonded samples with and without a Cr interlayer. This method provides a new idea for the integration of heterogeneous materials needed in wearable products and flexible printed circuits.

关键词： Wireless communication Integrated circuit technology Flexible printed circuits Atmosphere Metals Polyimides Nanoscale devices

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Ferroelectric materials, devices, and chips technologies for advanced computing and memory applications: development and challenges

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Science China(Information Sciences) 2025年第6期 118-173页

作者： Xiao YU Ni ZHONG Yan CHENG Tianjiao XIN Qing LUO Tiancheng GONG Jiezhi CHEN Jixuan WU Ran CHENG Zhiyuan FU Kechao TANG Jin LUO Tianling REN Fei XUE Lin CHEN Tianyu WANG Xueqing LI Xiuyan LI Ping WANG Xinqiang WANG Jie SUN Anquan JIANG Peiyuan DU Bing CHEN Chengji JIN Jiajia CHEN Haoji QIAN Wei MAO Siying ZHENG Huan LIU Haiwen XU Can LIU Zhihao SHEN Xiaoxi LI Bochang LI Zheng-Dong LUO Jiuren ZHOU Yan LIU Yue HAO Genquan HAN Hangzhou Institute of Technology Xidian University Faculty of Integrated Circuits Xidian University Key Laboratory of Polar Materials and Devices(MOE) Department of Electronics East China Normal University State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of Sciences School of Information Science and Engineering Shandong University College of Integrated Circuit Zhejiang University School of Integrated Circuits Southeast University School of Integrated Circuits Peking University School of Integrated Circuits Tsinghua University Center for Quantum Matter School of Physics Zhejiang University School of Microelectronics State Key Laboratory of Integrated Chips and Systems Fudan University Department of Electronic Engineering Tsinghua University National Key Laboratory of Micro and Nano Fabrication Technology and the Department of Micro-Nano Electronics Shanghai Jiao Tong University State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-Optoelectronics School of Physics Peking University Hangzhou Huarui Chip Innovation Technology Co. Ltd.

Hafnium（Hf） oxide-based ferroelectric materials have emerged as a transformative platform for next-generation non-volatile memory and advanced computing technologies. This review comprehensively examines the development, challenges, and applications of HfO2ferroelectrics, emphasizing their CMOS compatibility, scalability, and robust polarization at nanoscale dimensions. Breakthroughs in doping strategies, stress engineering, and VO control have stabilized the metastable orthorhombic phase, enabling high-performance devices such as ferroelectric RAM（FeRAM）, ferroelectric field-effect transistors（FeFETs）, and ferroelectric tunnel junctions（FTJs）. These devices offer ultrafast switching, low power consumption, and multi-level storage, driving innovations in neuromorphic computing, in-memory processing, and cryogenic systems; nonetheless, they face ongoing challenges in reliability, such as fatigue and imprint effects, and scalability at sub-5 nm technology nodes. Emerging frontiers, such as wurtzite-structured nitrides（e.g., AlScN） and antiferroelectric ZrO2-based systems, have garnered significant attention due to their exceptionally high remanent polarization and promising potential for enhanced endurance, respectively. Further addressing the reliability issues of these emerging ferroelectric materials and the challenges associated with large-scale integration processes through interdisciplinary efforts will unlock the full potential of ferroelectric technologies, positioning them as pivotal enablers of post-Moore computing architectures and sustainable AI-driven applications.

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In-depth Understanding of Polarization Switching Kinetics in Polycrystalline $\mathbf{Hf}_{0.5} \mathbf{Zr}_{0.5} \mathbf{O}_{2}$ Ferroelectric Thin Film: A Transition From NLS to KAI

In-depth Understanding of Polarization Switching Kinetics in...

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International Electron devices Meeting (IEDM)

作者： Wei Wei Weiqiang Zhang Lu Tai Guoqing Zhao Pengpeng Sang Qianwen Wang Fei Chen Mingfeng Tang Yang Feng Xuepeng Zhan Qing Luo Yuan Li Jiezhi Chen School of Information Science and Engineering Shandong University Qingdao China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665425735

To achieve deep insights into the polarization switching kinetics in ferroelectric $\text{Hf}0.5\text{Zr}0.5\mathrm{O}_{2}$ (HZO), the intrinsic switching characteristics are measured accurately by using a novel pulse sequence to eliminate the charge trapping, polarization unsaturation and imprint effects. By NLS fittings, the average switching time and the concentration of pinning sites are extracted, with main focus on their dependences on the external electric field, the electrode size $l$ and the temperature $T$ . Although the average switching time shows weak dependence on $T,$ , it decreases sharply with $l$ scaling and sub-ns switching behavior is predicted at $l\leq 3.89\mu \mathrm{m}$ . More importantly, our observations intensely imply that a transition happens from NLS to KAI model when $T$ is below 161K or $l$ is approaching the grain size (10~30nm). This surprised but reasonable transition indicates that, as scaling the ferroelectric memory size or for operations under cryogenic temperatures, HZO ferroelectrics can switch much faster and more uniform.

关键词： Electrodes Temperature dependence Voltage measurement Pulse measurements Switches Transforms Size measurement

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Dynamic neural network with memristive CIM and CAM for 2D and 3D vision

arXiv

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arXiv 2024年

作者： Zhang, Yue Zhang, Woyu Wang, Shaocong Lin, Ning Yu, Yifei He, Yangu Wang, Bo Jiang, Hao Lin, Peng Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100049 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100049 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China University of Chinese Academy of Sciences Beijing100049 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

The brain is dynamic, associative and efficient. It reconfigures by associating the inputs with past experiences, with fused memory and processing. In contrast, AI models are static, unable to associate inputs with past experiences, and run on digital computers with physically separated memory and processing. We propose a hardware-software co-design, a semantic memory-based dynamic neural network (DNN) using memristor. The network associates incoming data with the past experience stored as semantic vectors. The network and the semantic memory are physically implemented on noise-robust ternary memristor-based Computing-In-Memory (CIM) and Content-Addressable Memory (CAM) circuits, respectively. We validate our co-designs, using a 40nm memristor macro, on ResNet and PointNet++ for classifying images and 3D points from the MNIST and ModelNet datasets, which not only achieves accuracy on par with software but also a 48.1% and 15.9% reduction in computational budget. Moreover, it delivers a 77.6% and 93.3% reduction in energy consumption. © 2024, CC BY.

关键词： Memristors

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A Reconfigurable Mixed Signal CMOS Design for Multiple STDP Learning Rules

A Reconfigurable Mixed Signal CMOS Design for Multiple STDP ...

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International Conference on Electronics Technology (ICET)

作者： Chongyang Huan Yuan Wang Xiaoxin Cui Xing Zhang Key Laboratory of Microelectronics Devices and Circuits (MoE) Institute of Microelectronics Peking University Peking China

ISBN: (数字)9781728162836

ISBN: (纸本)9781728162843

Spike-timing-dependent-plasticity (STDP) is the learning algorithm for spiking neural network (SNN), which promises to obtain deeper understanding of biological neural system and more powerful artificial intelligence. However, most implementations for STDP learning rules have shortcomings in reconfigurability and richness. In this paper, a reconfigurable mixed-signal neuromorphic circuit for multiple STDP learning rules is proposed. Adopting phenomenological models, the design is easy to implement. Under a 65nm CMOS technology, simulation results show that the energy consumption for a weight update option is about 1~50 fJ/spike. The proposed circuit is suitable for neuromorphic applications using various STDP rules.

关键词： operational transconductance amplifier (OTA) neuromorphic engineering spike timing dependent plasticity (STDP) reconfigurability Neuromorphic engineering learning algorithms configurability Neuromorphics Learning energy consumption Rule

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The effect ofγ-ray irradiation on the SOT magnetic films and Hall devices

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Journal of Semiconductors 2021年第2期42卷 108-112页

作者： Tengzhi Yang Yan Cui Yanru Li Meiyin Yang Jing Xu Huiming He Shiyu Wang Jing Zhang Jun Luo Key Laboratory of Microelectronic Devices&Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences(IMECAS)Beijing 100029China University of Chinese of Academy Sciences(UCAS) Beijing 100049China School of Information Science and Technology North China University of TechnologyBeijing 100041China

Magnetoresistive random access memories(MRAMs)have drawn the attention of radiation researchers due to their potential high radiation *** particular,spin-orbit torque MRAM(SOT-MRAM)has the best performance on endurance and access speed,which is considered to be one of the candidates to replace SRAM for space ***,little attention has been given to theγ-ray irradiation effect on the SOT-MRAM device ***,we report the Co-60 irradiation results for both SOT(spin-orbit torque)magnetic films and SOT-Hall devices with the same *** properties of magnetic films are not affected by radiation even with an accumulated dose up to 300 krad(Si)while the magnetoelectronic properties of SOTHall devices exhibit a reversible change behavior during the *** propose a non-equilibrium anomalous Hall effect model to understand the *** results and proposed analysis in this work can be used for the material and structure design of memory cell in radiation-hardened SOT-MRAM.

关键词： SOT-MRAM γ-ray irradiation TID effect anomalous Hall effect

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A Physical Current Model for Multi-Finger Gate Tunneling FET with Schottky Junction

A Physical Current Model for Multi-Finger Gate Tunneling FET...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yimei Li Jin Luo Qianqian Huang Xia An Le Ye Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China Peking University Information Technology Institute (Tianjin Binhai)

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

Compared with conventional tunneling field-effect transistor (TFET), a novel multi-finger gate tunneling FET with Schottky junction (mFSB-TFET) can effectively obtain the steeper subthreshold slope due to tunneling electric field coupling effect, the higher I on due to the introduced multi-finger gate and Schottky junction, while keeping the ultra-low I off simultaneously. To facilitate the circuit simulation by using this new device, in this paper, we establish a physical model of the channel surface potential in both gate handle region and gate finger region, and then further calculate the tunneling current by considering tunneling electric field coupling effect and the Schottky current by considering the equivalent barrier reduction respectively. The model results with different structure parameters agree well with the Sentautus TCAD simulation results, which shows the validity of this model.

关键词： Semiconductor device modeling Couplings Simulation Tunneling Logic gates Junctions Electric fields

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High-Speed Trace Detection DROIC for 15μm-Pitch Cryogenic Infrared FPAs

High-Speed Trace Detection DROIC for 15μm-Pitch Cryogenic I...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Yuze Niu Yajun Zhu Wengao Lu Zhaofeng Huang Yuting Gu Yacong Zhang Zhongjian Chen Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics Peking University China Peking University information technology institute (Tianjin Binhai) China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper introduces a digital readout integrated circuit (DROIC) for 320×256 target-tracking infrared focal plane arrays(IRFPAs). The circuit is based on a two-stage ADC, which implements 10-bit coarse quantization and 4-bit fine quantization, enabling high frame frequency trace detection. In addition, the locating and independent output of sensitive pixels are realized by a scanning function, which greatly reduces output frequency and power consumption. The proposed ROIC of 15μm pixel-pitch is fabricated using 55nm 1P6M CMOS process. The pixel circuit consumes 379nW. Frame frequency of the target-tracking mode is 1 kHz, the two-stage ADC has a nonlinearity of 0.06%.

关键词： Quantization (signal) Capacitors Array signal processing Power demand Imaging Detectors Integrated circuits

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