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Vertical SnS2/Si heterostructure for tunnel diodes

Science China(Information Sciences) 2020年第2期63卷 189-195页

作者： Rundong JIA Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Tunneling FET（TFET） is considered as one of the most promising low-power electronic devices,however, suffers from the low drive current. Heterostructure TFET with low effective tunnel barrier height based on traditional 3D materials can obtain large tunnel current but deteriorated off-state current induced by the lattice mismatch. van der Waals heterostructure TFET based on 2D materials can obtain danglingbond-free interface for suppressed off-state current but face the challenge of controllable and stable doping technology. As the critical building block of the TFET, tunnel diode based on the 2D/3D heterostructure is proposed in this study and experimentally demonstrated. Combination of the pristine interface of 2D materials and matured doping technology in the traditional 3D bulk materials, tunnel diodes based on the 2D/3D heterostructures are expected to realize low leakage current and high on current simultaneously,showing great potential in low-power electronics. The N+SnS2/P+Si heterostructure with effective tunnel barrier of 0.17 eV theoretically is considered for the first time and selected as the optimal material platform for tunnel diodes. The N+SnS2/P+Si tunnel diode demonstrated experimentally shows the high current density of 1 μA/μm2, which is the highest one among the reported tunnel diodes based on the 2D/group IV materials. The tunneling current is also confirmed by low-temperature measurements. This study shows the great potential of the 2D/3D heterostructure for low-power tunneling devices.

关键词： 2D/3D heterostructure SnS2/Si tunnel barrier tunnel diode energy-efficient

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Low Power EEPROM Designed for Sensor Interface Circuit

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Chinese Journal of Electronics 2023年第4期21卷 642-644页

作者： Xiangyun MENG Sen YANG Zhongjian CHEN Wengao LU Yacong ZHANG Jingqing HUANG Haojiong LI Weiguo SU Song LI Department of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

EEPROM is an important part for interface circuit of sensor. It saves the calibration data and parameter setting data by non-volatile storage. A new low- power Erasable and electrically programmable read only memory (EEPROM) circuit for sensor interface circuit is introduced in this paper. The data stored in EEPROM can be reloaded automatically by the power-on-reset technique when the power is on. The module consumes power only during power-on-reset and data changing by status optimization and low-power design. This EEPROM circuit has been used in a MEMS accelerometer readout circuit verified by 0.35.μm CMOS EEPROM process. The results are satisfying in that the module can write and store 25bit data and automatically reloads data within 0.1.μs after power-on and then turns to low power mode.

关键词： Micromechanical devices Accelerometers Nonvolatile memory EPROM Calibration Research and development Optimization

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Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

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Journal of Semiconductors 2024年第1期45卷 33-37页

作者： Yang Feng Zhaohui Sun Yueran Qi Xuepeng Zhan Junyu Zhang Jing Liu Masaharu Kobayashi Jixuan Wu Jiezhi Chen School of Information Science and Engineering(ISE) Shandong UniversityQingdao 266200China Neumem Co. LtdHefei 230093China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of SciencesBeijing 100084China Institute of Industrial Science The University of TokyoTokyoJapan

With the rapid development of machine learning,the demand for high-efficient computing becomes more and more *** break the bottleneck of the traditional Von Neumann architecture,computing-in-memory(CIM)has attracted increasing attention in recent *** this work,to provide a feasible CIM solution for the large-scale neural networks(NN)requiring continuous weight updating in online training,a flash-based computing-in-memory with high endurance(10^(9) cycles)and ultrafast programming speed is *** the one hand,the proposed programming scheme of channel hot electron injection(CHEI)and hot hole injection(HHI)demonstrate high linearity,symmetric potentiation,and a depression process,which help to improve the training speed and *** the other hand,the low-damage programming scheme and memory window(MW)optimizations can suppress cell degradation effectively with improved computing *** after 109 cycles,the leakage current(I_(off))of cells remains sub-10pA,ensuring the large-scale computing ability of *** characterizations are done on read disturb to demonstrate its robust *** processing CIFAR-10 tasks,it is evident that~90%accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 *** results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training,which pave the way for further development of artificial intelligence(AI)accelerators.

关键词： NOR flash memory computing-in-memory endurance neural network online training

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High-quality and large-grain epi-like Si film by NiSi2-seed initiated lateral epitaxial crystallization（SILEC）

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Science China(Information Sciences) 2020年第12期63卷 272-274页

作者： Yuancheng YANG Baotong ZHANG Xiaoqiao DONG Xiaokang LI Shuang SUN Qifeng CAI Ran BI Xiaoyan XU Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Three-dimensional monolithic integration (3D-MI)has recently emerged for both "more Moore"and "more than Moore" applications, because of its high integration density, high bandwidth and multi-functions [1]. With 3D-MI, different types of devices can be stacked on the same platform and in a single process flow.

关键词： 3D monolithic integration (3D-MI) NiSi2-seed low-temperature crystallization epitaxial barrier layer metal contamination

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XOR spin logic operated by unipolar current based on field-free spin-orbit torque switching induced by a lateral interface

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Rare Metals 2024年第8期43卷 3868-3875页

作者： Yan-Ru Li Mei-Yin Yang Guo-Qiang Yu Bao-Shan Cui Jin-Biao Liu Yong-Liang Li Qi-Ming Shao Jun Luo Key Laboratory of Microelectronic Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences(IMECAS)Beijing 100029China University of Chinese Academy of Sciences(UCAS) Beijing 100049China Songshan Lake Materials Laboratory Dongguan 523808China Institute of Physics Chinese Academy of SciencesBeijing 100190China Key Laboratory for Magnetism and Magnetic Materials of Ministry of Education Lanzhou UniversityLanzhou 730000China Department of Electronic and Computer Engineering The Hong Kong University of Science and TechnologyHong Kong 999077China

Spin logics have emerged as a promising avenue for the development of logic-in-memory *** particular,the realization of XOR spin logic gates using a single spin-orbit torque device shows great potential for low-power stateful logic circuits in the next *** this study,we successfully obtained the XOR logic gate by utilizing a spin-orbit torque device with a lateral interface,which was created by local ion implantation in the Ta/Pt/Co/Ta Hall device exhibiting perpendicular magnetic *** angle of the lateral interface is set at 45°relative to the current direction,leading to the competition between symmetry breaking and current-driven Néel-type domain wall ***,the field-free magnetic switching reversed is realized by the same sign of current amplitude at this *** on this field-free magnetic switching behavior,we successfully proposed an XOR logic gate that could be implemented using only a single spin-orbit torque Hall *** study provides a potentially viable approach toward efficient spin logics and in-memory computing architectures.

关键词： Filed-free magnetic switching Spin-orbit torque XOR logic gate Lateral interface

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Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure

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Science China(Information Sciences) 2020年第4期63卷 245-247页

作者： Rundong JIA Liang CHEN Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Dear editor,Two-dimensional (2D) semiconductors have emerged as one of the most promising material candidates for next-generation electronic devices [1].Owing to the broad range of bandgap diversity and the pristine i... 详细信息

关键词： Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure VDS

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High Frame Rate High Linearity Low Power DROIC for 30μm-Pitch Cryogenic Infrared FPAs 14

High Frame Rate High Linearity Low Power DROIC for 30μm-Pit...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Niu, Yuze Gu, Yuting Liu, Fengqing Zhou, Fei Yu, Shanzhe Lu, Wengao Zhang, Yacong Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

This paper presents a pixel circuit with high frame rate, high linearity, and low power consumption. This pixel circuit is applied in a digital readout integrated circuit (DROIC) of 320×256 infrared focal plane array(IRFPA). The proposed single slope ADC is deployed in the proposed pixel circuit, which improves linearity and power consumption of the DROIC. The proposed pixel circuit is fabricated using 180nm 1P5M CMOS process with 30μm pixel pitch. Pixel power consumption is 406nW. Frame rate of the proposed DROIC is 1KHz. Nonlinearity of the quantization is lower than 0.8%. © 2021 IEEE.

关键词： Electric power utilization

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Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers 14

Low Power Readout Integrated Circuit with PFM-based ADCs Emp...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Zhou, Ye Yu, Shanzhe Lu, Wengao Yu, Dunshan Zhang, Yacong Chen, Zhongjian Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

This paper presents a low power readout integrated circuit (ROIC) with 12-bit two-stage column-wise ADCs for 25μm-pitch 640×480 silicon diode uncooled infrared imagers. A novel two-stage column-wise ADC composed of a pulse frequency modulation (PFM)-based ADC for coarse conversion and a single-slope ADC for fine conversion is proposed. The proposed ADC meets the requirements for power budget, conversion rate, and linearity performance in column-wise ADC application for uncooled infrared imagers. The PFM-based ADC adopts a passive integrator and an optimized comparator structure to reduce static power consumption. The ROIC is designed in standard 0.18μm 1P5M CMOS process. Simulation shows that the SNR and nonlinearity is 74dB and 0.12%, respectively. Power consumption of the ROIC is 54mW and each column ADC consumes only 10μW. © 2021 IEEE.

关键词： Budget control

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A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm Pitch 320 ×256 LWIR FPAs 14

A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm ...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Niu, Yuze Liu, Bingxin Kong, Jiaqi Zhou, Fei Yu, Shanzhe Lu, Wengao Zhang, Yacong Chen, Zhongjian Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

A low-power and high-dynamic range ADC-based 320×256 size digital readout integrated circuit for infrared focal plane arrays is proposed in this paper. Compared with the traditional structure, the proposed pixel-level ADC structure based on ring oscillator can achieve higher dynamic range and lower power consumption. The design is based on 0.18μm 1P5M CMOS process, and the pixel circuit pitch is 30μm. The simulation results show that the average power consumption of the proposed single pixel-level ADC is 1.36μW. The charge handling capacity of the pixel is 2.8Ge-;the dynamic range is 96.32dB, and the non-linearity is 0.76%. © 2021 IEEE.

关键词： Pixels

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A 9.1μW Capacitance-to-Digital Converter for Pressure Sensor Systems 16

A 9.1μW Capacitance-to-Digital Converter for Pressure Senso...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Xia, Qing-Jiang Zhang, Ya-Cong You, You Zhou, Fei Lu, Wen-Gao Peking University School of Software and Microelectronics Beijing100091 China Peking University Key Laboratory of Microelectronic Devices and Circuits Ministry of Education School of Integrated Circuits Beijing100871 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper presents a capacitance-to-digital converter (CDC) for pressure sensor systems, which consists of a front-end circuit and a successive approximation register (SAR) ADC. The front-end circuit uses correlated double sampling technology to eliminate the impact of the low-frequency noise and offset voltage of the operational amplifier. The CDACP and CDACN in the SAR ADC can save power and area as the sampling capacitance of the front-end circuit. The SAR ADC uses bottom plate sampling to avoid various nonlinearities caused by top plate sampling, and a comparator with pre-amplification to reduce the impact of kickback noise. Adjustable reference capacitance (CREF) is designed to expand the detection range of sensor capacitance. The circuit is designed and fabricated in 0.18μm standard CMOS process. While the power supply is 1.8V and the conversion time is 224μs, the power consumption is only 9.1μW. Capacitance resolution of 7.8fF is achieved with sensor capacitance (CSENS) detectable in the range of 10.1pF-21.5pF. © 2022 IEEE.

关键词： Pressure sensors

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