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China Semiconductor Technology International Conference (CSTIC)

作者： Zhiyuan Fu Cheng Chen Jin Luo Qianqian Huang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing CHINA

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, a ferroelectric-FET (FeFET) model based on multi-domain Preisach theory is developed. Instead of the single-domain Landau-Khalatnikvo (L-K) and tanh based model, the Preisach model with dynamic module is established to accurately model the dynamic behavior of multi-domain FeFET. Moreover, a FeFET-based neuron structure is presented and simulated based on the developed device model, showing the promising potential of FeFET for neuromorphic computing.

关键词： Semiconductor device modeling Neuromorphic engineering Computational modeling Neurons

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Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies

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Journal of Semiconductors 2025年第6期46卷 66-78页

作者： Yu Song Pengfei Jiang Pan Xu Xueyang Peng Qianqian Wei Qingyi Yan Wei Wei Yuan Wang Xiao Long Tiancheng Gong Yang Yang Eskilla Venkata Ramana Qing Luo Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of SciencesBeijing 100029China Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 101408China I3N-Aveiro Department of PhysicsUniversity of AveiroAveiro3810193Portugal

The novel HfO2-based ferroelectric field effect transistor(FeFET)is considered a promising candidate for next-genera-tion nonvolatile memory(NVM).However,a series of reliability issues caused by the fatigue effect hinder its further ***,a comprehensive understanding of the fatigue mechanisms of the device and optimization strategies is essen-tial for its *** fundamental mechanism of the fatigue effect is attributed to charge trapping and trap generation based on the current studies,and the underlying causes,occurrence locations and specific impacts are analyzed in this *** particular,the asymmetric trapping/detrapping of electrons and holes,as well as the relationship between the ferroelectric(FE)polarization and charge trapping,are given particular *** categorizing and summarizing the current progress,we propose a series of optimization strategies derived based on the fatigue mechanisms.

关键词： FeFET fatigue charge trapping trap generation

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Super-Heisenberg scaling in a triple point criticality

arXiv

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arXiv 2024年

作者： Cheng, Jia-Ming Zhang, Yong-Chang Zhou, Xiang-Fa Zhou, Zheng-Wei Xi’an Microelectronics Technology Institute Xi’an710065 China MOE Key Laboratory for Nonequilibrium Synthesis and Modulation of Condensed Matter Shaanxi Key Laboratory of Quantum Information and Quantum Optoelectronic Devices School of Physics Xi’an Jiaotong University Xi’an710049 China CAS Key Lab of Quantum Information University of Science and Technology of China Hefei230026 China Synergetic Innovation Center of Quantum Information and Quantum Physics University of Science and Technology of China Hefei230026 China

We investigate quantum-enhanced metrology in a triple point criticality and discover that quantum criticality does not always enhance measurement precision. We have developed suitable adiabatic evolution protocols to effectively restrain excitations, which could accelerate the adiabatic evolutions and lead to an exponential super-Heisenberg scaling. This scaling behavior is quite valuable in practical parameter estimating experiments with limited coherence time. Dissipation can strengthen the super-Heisenberg scaling until decoherence increases to dominate in the dissipative dynamics. Additionally, measurement precisions beyond Heisenberg scaling can be experimentally achieved in the trapped ion system. Our findings strongly indicate that criticality-enhanced metrology can indeed significantly enhance measurement precisions to a super-Heisenberg scaling when combining a triple point and beneficial parameter modulations, which will be conducive to the exploration of other super-Heisenberg scaling and their applications. © 2024, CC BY-NC-ND.

关键词： Criticality (nuclear fission)

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Interfacial properties of 2DWS2on SiO2substrate from x-ray photoelectron spectroscopy and first-principles calculations

arXiv

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arXiv 2022年

作者： Zhou, Changjie Zhu, Huili Yang, Weifeng Lin, Qiubao Zheng, Tongchang Yang, Lan Lan, Shuqiong Xiamen Key Laboratory of Ultra-Wide Bandgap Semiconductor Materials and Devices Department of Physics School of Science Jimei University Xiamen361021 China Department of Microelectronics and Integrated Circuits Xiamen University Xiamen361005 China

Two-dimensional (2D) WS2films were deposited on SiO2wafers, and the related interfacial properties were investigated by high-resolution x-ray photoelectron spectroscopy (XPS) and first-principles calculations. Using the direct (indirect) method, the valence band offset (VBO) at monolayer WS2/SiO2interface was found to be 3.97 eV (3.86 eV), and the conduction band offset (CBO) was 2.70 eV (2.81 eV). Furthermore, the VBO (CBO) at bulk WS2/SiO2interface is found to be about 0.48 eV (0.33 eV) larger due to the interlayer orbital coupling and splitting of valence and conduction band edges. Therefore, the WS2/SiO2heterostructure has a Type I energy-band alignment. The band offsets obtained experimentally and theoretically are consistent except the narrower theoretical bandgap of SiO2. The theoretical calculations further reveal a binding energy of 75 meV per S atom and the totally separated partial density of states, indicating a weak interaction and negligible Fermi level pinning effect between WS2monolayer and SiO2surface. Our combined experimental and theoretical results provide proof of the sufficient VBOs and CBOs and weak interaction in 2D WS2/SiO2heterostructures. Copyright © 2022, The Authors. All rights reserved.

关键词： Silica

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An 81–99 GHz Tripler with Fundamental Cancellation and 3rd Harmonic Enhancement Technique in 40-nm CMOS

An 81–99 GHz Tripler with Fundamental Cancellation and 3rd ...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiaolei Su Xiucheng Hao Dong Wang Zhengkun Shen Zexue Liu Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

An 81–99 GHz tripler for wireless transceiver LO generation is presented in this paper. To suppress the fundamental signal and enhance the 3rd harmonic, the inversion signal is applied to the gate of the cascading transistor of the push-push differential pair. A capacitor is connected to the source and drain of the cascading transistor to further suppress the fundamental signal. Without additional filters, the tripler achieves more than 40 dBc of fundamental suppression with an even harmonic suppression of up to 60 dBc. The tripler reaches an output power of −2.6 dBm (4-dBm input) at 91.5 GHz with a 20% bandwidth of from 81 to 99 GHz. The core area of the chip occupies only 190 μm×530 μm in TSMC 40-nm CMOS process and consumes 28.2 mW.

关键词： Harmonic analysis Power harmonic filters Transistors Radio frequency Parasitic capacitance Capacitors Inductors

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A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection

A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC w...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiaolong Chen Enbin Gong Hao Zhang Le Ye Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking university Beijing 100871 China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper proposed a pseudo-open boost DC-DC converter whose input voltage ranges from 300mV-to-500mV and output voltage ranges from 1.2V-to-1.8V. The output power ranges from 1μW to 158μW. Three key structures are designed to realize the high energy conversion efficiency when the load reaches ultra-light: the pseudo open-loop structure, the frequency-programmable oscillator, and the hybrid zero current detection (H-ZCD) circuit. The pseudo open-loop structure eliminates the analog comparators or error amplifiers used in converter and the quiescent power loss is much reduced. The frequency-programmable ring oscillator is able to output 9-bit binary frequency ranges from 500Hz-100KHz, so the power consumption of clock generation is saved when load power reaches to ultra-light. The proposed H-ZCD is designed to reduce the inductor power loss with just tiny power consumption. Accordingly, the high efficiency boost DC-DC works in the discontinuous condition mode (DCM) and the constant on time pulse frequency modulation (PFM) is proposed. As a simulation result, the peak efficiency of the converter reaches to 86.7% while the load power is 13.7μW.

关键词： Ring oscillators DC-DC power converters Power demand Switches Capacitors Energy efficiency

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Low power and high uniformity of HfOx-based RRAM via tip-enhanced electric fields

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中国科学:化学（英文版） 2019年第10期62卷 160-166页

作者： Xiaokang LI Baotong ZHANG Bowen WANG Xiaoyan XU Yuancheng YANG Shuang SUN Qifeng CAI Shijie HU Xia AN Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking University Beijing 100871 China

In this paper,the HfOx-based resistive random access memory (RRAM) devices with sub-100 nm pyramid-type electrodes were *** the help of tip-enhanced electric field around the pyramid-type electrodes,it was experimentally demonstrated that the novel devices have better cycle-to-cycle variation control,lower forming/set voltage (1.97/0.7 V) and faster switching speed (≤ 30 ns under 0.9 V pulse) as well as better endurance reliability than conventional flat electrode resistive memory *** addition,the novel RRAM is experimentally demonstrated with independence of electrode number for the first time to present great potential in scaling *** novel structure metal-oxide based RRAM will be suitable for the future low-power non-volatile memory application.

关键词： RRAM pyramid-type electrode variation reliability switching speed conducting filament

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A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique

A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source Wi...

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作者： Liang, Yuan Boon, Chirn Chye Qi, Gengzhen Dziallas, Giannino Kissinger, Dietmar Ng, Herman Jalli Mak, Pui-In Wang, Yong Nanyang Technological University School of Electrical and Electronic Engineering Singapore639798 Singapore Sun Yat-sen University School of Microelectronics Science and Technology Zhuhai519082 China State-Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics University of Macau China Leibniz Institute for High Performance Microelectronics Frankfurt an der Oder 15236 Germany Institute of Electronic Devices and Circuits Ulm University Ulm89081 Germany Karlsruhe University of Applied Sciences Faculty of Electrical Engineering and Information Technology Karlsruhe76133 Germany University of Electronic Science and Technology of China School of Information and Communication Engineering Chengdu611731 China Nanhu Laboratory Jiaxing314002 China

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- N phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- \mu \text{m} SiGe BiCMOS technology, the proposed signal source shows a -73.1-dBc reference spur, -113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and -90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fsrms at 40.96 GHz and 122 fsrms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is -3.24 dBm, and the power consumption is 372 mW. © 1963-2012 IEEE.

关键词： Phase locked loops

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Thermalization Effect in semiconductor Si, and metallic silicide NiSi2, CoSi2 by using Non-Adiabatic Molecular Dynamics Approach

arXiv

引用

arXiv 2023年

作者： Luo, Kun Gan, Weizhuo Hou, Zhaozhao Zhan, Guohui Xu, Lijun Liu, Jiangtao Lu, Ye Wu, Zhenhua Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China School of Integrated Circuits University of Chinese Academy of Sciences Beijing100049 China HiSilicon Technologies Shenzhen China College of Mechanical and Electrical Engineering Guizhou Minzu University Guiyang550025 China The School of Information Science and Technology Fudan University Shanghai200433 China

Recently, cold source transistor (CSFET) with steep-slope subthreshold swing (SS) 2 and CoSi2). The dependence of the thermalization factor, relaxation time, scattering time and scattering rate on energy level are obtained. The thermalization of carrier gradually increases from low energy to high energy. Partially thermalization from the ground state to reach the thermionic current window is realized with sub-100 fs time scale. Fully thermalization to entail energy region depends on the barrier height sensitively, i.e., the scattering rate decreases exponentially as the energy of the out-scattering state increase. The scattering rate of NiSi2 and CoSi2 is 2 orders of magnitude higher than that of Si, arising from their higher density of states than that in Silicon This study can shed light on the material design for low power tunneling FET as well as the emerging CSFET. Copyright © 2023, The Authors. All rights reserved.

关键词： Silicides

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Quantum transport quality of a processed undoped Ge/SiGe heterostructure

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Physical Review B 2023年第4期108卷 045303-045303页

作者： Yi-Xin Li Zhenzhen Kong Shimin Hou Guilei Wang Shaoyun Huang Beijing Key Laboratory of Quantum Devices Key Laboratory for the Physics and Chemistry of Nanodevices Peking University Beijing 100871 People's Republic of China Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 People's Republic of China School of Integrated Circuits University of Chinese Academy of Sciences Beijing 100049 People's Republic of China Hefei National Laboratory Hefei 230088 People's Republic of China and Beijing Superstring Academy of Memory Technology Beijing 100176 People's Republic of China

A degraded mobility of 5.2×105cm2V−1s−1 but a long quantum scattering time of 2.3 ps at the hole density of 2.25×1011cm−2 were obtained from a two-dimensional hole gas in a processed undoped Ge/SiGe heterostructure Hall-bar field-effect device. The heterostructure was grown by the reduced pressure chemical vapor deposition method and the device fabrications were compatible with well-established semiconductor technology. The percolation density of 0.69×1011cm−2 indicated a very low disorder potential landscape experienced by holes in the strained Ge quantum well. In addition to integer quantum Hall effects (IQHEs) of consecutive filling factors from ν=8 down to 1, we also observed the quantum states at filling factors between ν=1 and 2, and between ν=2 and 3 at 1.71 K. The observation of quantum Hall effects at the inferior mobility confirmed the mobility/quality dichotomy in the ultraclean undoped Ge/SiGe heterostructure. The study explicitly indicated that the device fabrication process likely compromised the transport mobility, whereas the quantum quality was less influenced, and established the heterostructure as an ideal platform for quantum device implementations.

关键词： Electrical properties Fractional quantum Hall effect Quantum Hall effect Quantum wells Two-dimensional electron system Epitaxy Hall bar Methods in transport Shubnikov-de Haas effect

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