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Vertical SnS2/Si heterostructure for tunnel diodes

Science China(Information Sciences) 2020年第2期63卷 189-195页

作者： Rundong JIA Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Tunneling FET（TFET） is considered as one of the most promising low-power electronic devices,however, suffers from the low drive current. Heterostructure TFET with low effective tunnel barrier height based on traditional 3D materials can obtain large tunnel current but deteriorated off-state current induced by the lattice mismatch. van der Waals heterostructure TFET based on 2D materials can obtain danglingbond-free interface for suppressed off-state current but face the challenge of controllable and stable doping technology. As the critical building block of the TFET, tunnel diode based on the 2D/3D heterostructure is proposed in this study and experimentally demonstrated. Combination of the pristine interface of 2D materials and matured doping technology in the traditional 3D bulk materials, tunnel diodes based on the 2D/3D heterostructures are expected to realize low leakage current and high on current simultaneously,showing great potential in low-power electronics. The N+SnS2/P+Si heterostructure with effective tunnel barrier of 0.17 eV theoretically is considered for the first time and selected as the optimal material platform for tunnel diodes. The N+SnS2/P+Si tunnel diode demonstrated experimentally shows the high current density of 1 μA/μm2, which is the highest one among the reported tunnel diodes based on the 2D/group IV materials. The tunneling current is also confirmed by low-temperature measurements. This study shows the great potential of the 2D/3D heterostructure for low-power tunneling devices.

关键词： 2D/3D heterostructure SnS2/Si tunnel barrier tunnel diode energy-efficient

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A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight

A Spiking Neural Network Accelerator based on Ping-Pong Arch...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Zilin Wang Yi Zhong Xiaoxin Cui Yisong Kuang Yuan Wang Key Laboratory of Microelectronics Devices and Circuits (MoE) MPW Center School of Integrated Circuits Peking University Beijing China

Spiking neural networks (SNNs) have attracted widespread interest due to their event-driven and low-power nature. Compared to Artificial Neural Networks (ANNs), SNNs have time dimension information and present more realistic brain-inspired computing models. However, it is challenging to deploy sparse spiking neuron network models on dense neuromorphic processors. In this paper, a spiking neural network accelerator with sparse spike and weight is presented, using ping-pong architecture to improve system data throughput. To reduce the inference delay, the proposed accelerator supports the decoupling of calculation of membrane potential and leaky integrate-and-fire (LIF) dynamics computing in the feedforward neural networks. Implemented on Xilinx Kintex UltraScale FPGA, the accelerator can achieve the peak performance of 65.7 GSOP/s and the energy efficiency of 41.7 GSOP/W in the task of classifying MNIST dataset. Under the full load, the whole system can run ping-pong when more than 43 time steps are calculated at a time.

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Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure

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Science China(Information Sciences) 2020年第4期63卷 245-247页

作者： Rundong JIA Liang CHEN Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Dear editor,Two-dimensional (2D) semiconductors have emerged as one of the most promising material candidates for next-generation electronic devices [1].Owing to the broad range of bandgap diversity and the pristine i... 详细信息

关键词： Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure VDS

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Assessing high-energy x-ray and proton irradiation effects on electrical properties of P-GaN and N-GaN thin films

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Chinese Physics B 2023年第7期32卷 443-447页

作者：钟傲雪王磊唐蕴杨永涛王进进朱慧平吴真平唐为华李博 State Key Laboratory of Information Photonics and Optical Communications&School of Science Beijing University of Posts and TelecommunicationsBeijing 100876China Institute of Microelectronics and Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of SciencesUniversity of Chinese Academy of SciencesBeijing 100029China School of Integrated Circuits&State Key Laboratory of Information Photonics and Optical Communications Beijing University of Posts and TelecommunicationsBeijing 100876China

The effects of ionizing and displacement irradiation of high-energy x-ray and 2-MeV proton on GaN thin films were investigated and compared in this *** electrical properties of both P-GaN and N-GaN,separated from power devices,were gauged for fundamental *** was found that the electrical properties of P-GaN were improved as a consequence of the disruption of the Mg-H bond induced by high-dose x-ray irradiation,as indicated by the Hall and circular transmission line ***,under a 100-Mrad(Si)x-ray dose,the specific contact resistance pc of P-GaN decreased by 30%,and the hole carrier concentration increased ***,the atom displacement damage effect of a 2-MeV proton of 1×10^(13)p/cm^(2)led to a significant degradation of the electrical properties of P-GaN,while those of N-GaN remained unchanged.P-GaN was found to be more sensitive to irradiation than N-GaN thin *** effectiveness of x-ray irradiation in enhancing the electrical properties of P-GaN thin films was demonstrated in this study.

关键词： x-ray radiation proton radiation GaN circular transmission line model(CTLM)

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NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing

NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture ...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Yi Zhong Zilin Wang Yipeng Gao Xiaoxin Cui Xing Zhang Yuan Wang School of Integrated Circuits Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China Key Laboratory of Microelectronics Devices and Circuits (MoE) MPW Center Peking University Beijing China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Neuromorphic computing has endeavored a novel computing paradigm that entails a bio-inspired architecture to reproduce the remarkable functionalities of the human brain, such as massively parallel processing and extremely low-power consumption. However, those promising merits can be greatly canceled by the mismatched communication infrastructure in large-scale hardware implementation, in view of the vast degree of neural connectivity, the unstructured spike dataflow, and the unbalanced model workload assignment. In an effort to tackle those challenges, this work presents NeuroHexa, a network-on-chip (NoC) architecture intended for multi-core neuromorphic design. NeuroHexa adopts a customized intra-chip hexagonal topology, which can be further cascaded in 6 directions by either 2D or 3D chiplet integration. Designed in globally asynchronous, locally synchronous (GALS) methodology, a group of processing nodes can operate in independent work pace to further improve resource utilization. To satisfy the varied requirement of data reuse across the chip, NeuroHexa proposes a flexible multicast routing mechanism to best adapt to the model-defined dataflow. And under a specific congestion scenario, NeuroHexa can switch its routing algorithm between deterministic routing and fully adaptive routing modes. The presented NoC router is evaluated in 28nm CMOS, where we achieve the maximal throughput as 179.2Gbps, and the best energy efficiency as 4.872pJ/packet at the area overhead of 0.0226mm 2 .

关键词： Semiconductor device modeling Adaptation models Three-dimensional displays Neuromorphic engineering Unicast Computer architecture Routing Throughput Topology Resource management

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Low Power EEPROM Designed for Sensor Interface Circuit

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Chinese Journal of Electronics 2023年第4期21卷 642-644页

作者： Xiangyun MENG Sen YANG Zhongjian CHEN Wengao LU Yacong ZHANG Jingqing HUANG Haojiong LI Weiguo SU Song LI Department of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

EEPROM is an important part for interface circuit of sensor. It saves the calibration data and parameter setting data by non-volatile storage. A new low- power Erasable and electrically programmable read only memory (EEPROM) circuit for sensor interface circuit is introduced in this paper. The data stored in EEPROM can be reloaded automatically by the power-on-reset technique when the power is on. The module consumes power only during power-on-reset and data changing by status optimization and low-power design. This EEPROM circuit has been used in a MEMS accelerometer readout circuit verified by 0.35.μm CMOS EEPROM process. The results are satisfying in that the module can write and store 25bit data and automatically reloads data within 0.1.μs after power-on and then turns to low power mode.

关键词： Micromechanical devices Accelerometers Nonvolatile memory EPROM Calibration Research and development Optimization

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A Fully BEOL-compatible (300°C Annealing) IGZO FeFET with Ultra-high Memory Window (10V) and Prominent Endurance (109)

A Fully BEOL-compatible (300°C Annealing) IGZO FeFET with U...

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2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Xu, Pan Jiang, Pengfei Yang, Yang Peng, Xueyang Wei, Wei Gong, Tiancheng Wang, Yuan Long, Xiao Niu, Jiebin Xu, Zhongguang Zhu, Chenxin Wu, Zhenhua Luo, Qing Liu, Ming Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China University of Science and Technology of China Anhui Hefei China

ISBN: (纸本)9798350365429

HfO2-based FeFET paves the way for the next generation NVM thecnology, however, demands for high memory window (MW) and roubust reliability (especially the endurance) cannot be combined in the current reported devices, and the contradiction of high MW and low thermal budget (aiming for BEOL compatibility) also needs to be solved. In this work, we propose an integrated ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) and amorphous In-Ga-Zn-O (a- IGZO) channel FeFET with a maximum 10V MW and prominent endurance up to 109. Workfunction (WF) engineering is utilized to regualtethe intrinsic Vt to improve the PGM/ERS efficiency with full-loop polarization switching, and the adopted Mo gate can effectively reduce the thermal budget to 300°Censuringa fully BEOL compatibility. Then with O3-plasma treatment to the gate electrode, the introduced tunneling layer can futher improve the MW by gate charge injection. The demonstrated FeFET shows great 3-bit/cell storage ability without states overlapping, high Ion/Ioff ratio (>107), as well as great linearity and high Gmax/Gmin (286) during synaptic weight modulation. © 2024 IEEE.

关键词： Budget control

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Interfacial properties of 2D WS_(2)on SiO_(2)substrate from X-ray photoelectron spectroscopy and firstprinciples calculations

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Frontiers of physics 2022年第5期17卷 93-103页

作者： Changjie Zhou Huili Zhu Weifeng Yang Qiubao Lin Tongchang Zheng Lan Yang Shuqiong Lan Xiamen Key Laboratory of Ultra-Wide Bandgap Semiconductor Materials and Devices Department of PhysicsSchool of ScienceJimei UniversityXiamen 361021China Department of Microelectronics and Integrated Circuits Xiamen UniversityXiamen 361005China

Two-dimensional(2D)WS_(2)films were deposited on SiO_(2)wafers,and the related interfacial properties were investigated by high-resolution X-ray photoelectron spectroscopy(XPS)and first-principles *** the direct(indirect)method,the valence band offset(VBO)at monolayer WS_(2)/SiO_(2)interface was found to be 3.97 eV(3.86 eV),and the conduction band offset(CBO)was 2.70 eV(2.81 eV).Furthermore,the VBO(CBO)at bulk WS_(2)/SiO_(2)interface is found to be about 0.48 eV(0.33 eV)larger due to the interlayer orbital coupling and splitting of valence and conduction band ***,the WS_(2)/SiO_(2)heterostructure has a Type I energy-band *** band offsets obtained experimentally and theoretically are consistent except the narrower theoretical bandgap of SiO_(2).The theoretical calculations further reveal a binding energy of 75 meV per S atom and the totally separated partial density of states,indicating a weak interaction and negligible Fermi level pinning effect between WS_(2)monolayer and SiO_(2)*** combined experimental and theoretical results provide proof of the sufficient VBOs and CBOs and weak interaction in 2D WS_(2)/SiO_(2)heterostructures.

关键词： band offsets WS_(2) SiO_(2) X-ray photoelectron spectroscopy first-principles calculations

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Investigation of Electrical Characteristics on Morphotropic Phase Boundary of Hf1-xZrxO2for Dynamic Random Access Memories

Investigation of Electrical Characteristics on Morphotropic ...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Zhong, Kun Yin, Huaxiang Zhang, Zhaohao Zhang, Fan Key Laboratory of Microelectronics Devices and Integrated Technology China Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China Xidian University Key Laboratory of Wide Bandgap Semiconductor Materials China School of Integrated Circuits University of Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9798350311006

This paper investigates the properties of different Zr compositions in Hf1-xZrxO2 films. Due to the morphotropic phase boundary (MPB) between the orthorhombic ferroelectric phase and the tetragonal anti-ferroelectric phase, a maximum κ value of 55 was obtained for 9 nm Hf0.4Zr0.6O2 films. Furthermore, the sufficiently low leakage current of the capacitors was confirmed. Finally, a promising switching endurance of up to 5× 109 cycles was also performed, which becomes one of the driving forces for next-generation dynamic random access memories (DRAM) cell capacitor dielectric materials. © 2023 IEEE.

关键词： Ferroelectricity

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Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction

Experimental Demonstration of A CT-FeFET Array with Intrinsi...

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2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Li, Chao Yu, Jie Zhang, Xumeng Zhang, Zhaohao Zhu, Fangduo Ouyang, Siyuan Chen, Pei Cheng, Lingli Xu, Gaobo Zhang, Qingzhu Yin, Huaxiang Liu, Qi Liu, Ming State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200438 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9798350365429

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000× and 4× improvements than GPU in power consumption and memory overhead. © 2024 IEEE.

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