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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012

作者： Li, Min Lin, Meng Yun, Quanxin Li, Zhiqiang An, Xia Li, Ming Zhang, Xing Ru, Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781467324724

The effect of CHF3 gas flow rate on the trench shape and etch rate was studied for germanium-based device fabrication. In this study, a sidewall tilt angle larger than 80° with the trench depth of 300nm was achieved by optimizing the flow rate ratio of SF6/CHF3/He gas mixture. Then, based on the experimental results, a Linear Reactive Ion Etching (RIE) Model was proposed to predict the optimized composition of the SF6/CHF3/He gas mixture to obtain steep trenches with low etch rate, which may provide the guideline for the germanium etching process design. © 2012 IEEE.

关键词： Sulfur hexafluoride

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Investigation on Channel Hot Carrier degradation of ultra deep submicron SOI pMOSFETs

Investigation on Channel Hot Carrier degradation of ultra de...

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012

作者： Huang, Liang-Xi An, Xia Tan, Fei Wu, Wei-Kang Ru, Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 Beijing China

ISBN: (纸本)9781467324724

The bias dependence of Channel Hot Carrier (CHC) degradation in 0.18μm SOI pMOSFETs is investigated in this paper. Two classical bias modes (V g@Isubmax and Vg=Vd) were applied to analyze the CHC degradation behavior of SOI pMOSFETs. The results show that at low Vg, hot carriers injection produced by impact ionization is the main factor contributed to degradation. However, the degradation stressed at high Vg is controlled by both CHC and NBTI effect, showing the NBTI-like behavior at room temperature which indicates that NBTI effect is the dominant factor. A possible mechanism is put forward to explain the enhanced CHC degradation under Vg=Vd compared with pure NBTI degradation. The influence of floating body on the performance degradation of PDSOI devices is also investigated. © 2012 IEEE.

关键词： Negative bias temperature instability

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Heavy-ion-induced permanent damage in ultra-deep submicron fully depleted SOI devices

Heavy-ion-induced permanent damage in ultra-deep submicron f...

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012

作者： Tan, Fei An, Xia Huang, Liangxi Zhang, Xing Ru, Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 Beijing China

ISBN: (纸本)9781467324724

In this paper, heavy-ion-induced permanent damage in fully depleted silicon-on-insulator (FD SOI) devices are investigated. After exposure to heavy ions, the characteristics degradation of FD SOI nMOSFET are presented, which is due to the microdose effect in the oxide layer and the displacement damage in silicon film. Besides, the measured results also exhibit strong device geometry dependence. The electrical properties degradation such as the off-state leakage current and the on-state current become more serious with the gate length or gate width decreasing, which indicates that the heavy-ion-induced damage in ultra-deep submicron FD SOI devices can not be ignored and should be paid more attention for radiation hardened applications. © 2012 IEEE.

关键词： Heavy ions

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Clock Controlled Hybrid-latch flip-flops Design

Clock Controlled Hybrid-latch flip-flops Design

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Jia Song Yan Shilin Wu Fengfeng Wang Yuan Key Laboratory of Microelectronics Devices and Circuits(MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467324748

In order to obtain power efficient flip-flops,two novel Hybrid-latch schemes are introduced in this paper. They achieve high performance by shortening the critical data path and power efficiency by eliminating the inverter chain pulse *** simulation under SMIC 90nm process revealed that the two new flip-flop have excellent power and speed performance compared to the referenced *** can reduce 44.5% and 51.4% power dissipation,29.2% and 44.5% clock-to-output latency and 65.6% and 68.4% PDP.

关键词： simulation Hybrid Clock Controlled Hybrid-latch flip-flops Design PDP

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Selective Parallel CRC Computation Schemes for RapidIO

Selective Parallel CRC Computation Schemes for RapidIO

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Wu Fengfeng Jia Song Xu Heqing Wang Yuan Zhang Dacheng Key Laboratory of Microelectronics Devices and Circuits（MOE） Institute of Microelectronics Peking University

ISBN: (纸本)9781467324748

RapidIO is a high-performance standard for embedded *** to different ending alignments of RapidIO packets,the corresponding CRC computations should be *** this paper,two selective parallel computation schemes based on simplified intermediate value equations are *** with the reference designs,the power dissipations can be reduced by more than 30% meanwhile better balances between the speeds and resource consumptions can be achieved.

关键词： achieved speeds consumptions

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Contact size scaling of a W-contact phase-change memory cell based on numerical simulation

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Journal of Semiconductors 2012年第10期33卷 53-57页

作者：魏益群林信南贾宇超崔小乐张兴宋志棠 Key Laboratory of Integrated Microsystems Shenzhen Graduate School of Peking University TSRC Key Laboratory of Microelectronic Devices and CircuitsInstitute of MicroelectronicsSchool of Electronics and Computer SciencePeking University State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Microsystem and Information TechnologyChinese Academy of Sciences

In the design of phase-change memory（PCM）,it is important to perform numerical simulations to predict the performances of different device *** work presents a numerical simulation using a coupled system including Poisson＇s equation,the current continuity equation,the thermal conductivity equation,and phase-change dynamics to simulate the thermal and electric characteristics of phase-change *** method discriminates the common numerical simulation of PCM cells,from which it applies Possion＇s equation and current continuity equations instead of the Laplace equation to depict the electric characteristics of PCM cells,which is more adoptable for the semiconductor characteristics of phase-change *** results show that the simulation agrees with the measurement,and the scalability of PCM is predicted.

关键词： phase-change memory scaling numerical simulation

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A Power Clamp Circuit Using Current Mirror for On-chip ESD Protection

A Power Clamp Circuit Using Current Mirror for On-chip ESD P...

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Guangyi Lu Yuan Wang Xuelin Zhang Song Jia Ganggang Zhang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits(MoE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467324748

A power clamp circuit using current mirror is proposed in this *** current mirror is used for capacitance multiplication in the proposed circuit. Besides,the proposed circuit has different turn-on and turn-off paths towards clamp transistor and it employs a non-traditional phase inverter in the turn-on path of clamp *** results verify that the proposed circuit has enhanced ability to discharge static charges during an ESD event while making the ESD pulse detection CR time constant notably *** the reduction of CR time constant,the proposed circuit has better immunity to mis-triggering and is less chip area-consuming.

关键词： Electrostatic discharge(ESD),power clamp circuit,current mirror,mis-triggering

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A 150%enhancement of PMOSFET mobility using hybrid orientation

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Journal of Semiconductors 2012年第6期33卷 20-23页

作者：唐昭焕谭开洲崔伟张静钟怡徐世六郝跃张鹤鸣胡辉勇张正璠胡刚毅 Science and Technology on Analog Integrated Circuit Laboratory Sichuan Institute of Solid-State Circuits China Electronics Technology Group Corp Key Laboratory of the Ministry of Education for Wide-Band Gap Semiconductor Materials and Devices School of MicroelectronicsXidian University

A high-performance PMOSFET based on silicon material of hybrid orientation is *** orientation wafers,integrated by（100） and（110） crystal orientation,are fabricated using silicon-silicon bonding, chemical mechanical polishing,etching silicon and non-selective expitaxy.A PMOSFET with W/L = 50μm/8μm is also processed,and the measured results show that the drain-source current and peak mobility of the PMOSFET are enhanced by up to 50.7%and 150%at V_（gs） =-15 V and V_（ds） =-0.5 V,*** mobility values are higher than that reported in the literature.

关键词： hybrid orientation non-selective expitaxy carrier mobility （110） crystal orientation PMOSFET chemical mechanical polishing

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A SPICE model for a phase-change memory cell based on the analytical conductivity model

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Journal of Semiconductors 2012年第11期33卷 52-56页

作者：魏益群林信南贾宇超崔小乐何进张兴 The Key Laboratory of Integrated Microsystems Shenzhen Graduate School of Peking University Peking University Shenzhen SOC Key Laboratory PKU-HKUSTShenzhen-Hong Kong Institute The Kev Laboratorv of Integrated Microsvstems.Shenzhen Graduate School of Peking University Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsSchool of Electronics and Computer SciencePeking University

By way of periphery circuit design of the phase-change memory,it is necessary to present an accurate compact model of a phase-change memory cell for the circuit *** with the present model,the model presented in this work includes an analytical conductivity model,which is deduced by means of the carrier transport theory instead of the fitting model based on the *** addition,this model includes an analytical temperature model based on the 1D heat-transfer equation and the phase-transition dynamic model based on the JMA equation to simulate the phase-change *** above models for phase-change memory are integrated by using Verilog-A language,and results show that this model is able to simulate theⅠ-Ⅴcharacteristics and the programming characteristics accurately.

关键词： phase-change memory compact model analytical conductivity

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Enhanced Nitrogen Plasma Immersion Passivation Method for High-K/Ge Stack Formation

Enhanced Nitrogen Plasma Immersion Passivation Method for Hi...

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2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Meng Lin Quanxin Yun Min Li Zhiqiang Li Xia An Ming Li Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper,an enhanced Ge surface passivation method by nitrogen plasma immersion with adding RIE power is presented and experimentally demonstrated. With the acceleration effect resulting from electric field induced by proper RIE power,more nitrogen plasma will drift to Ge surface to passivate the dangling *** is shown that nitrogen plasma immersion with RIE power is efficient in suppressing Ge suboxide growth during high-K dielectric deposition,reducing interface states and improving the C-V characteristic of both p-MOS and n-MOS capacitors in terms of flat-band voltage and hysteresis.

关键词： MOS RIE Enhanced Nitrogen Plasma Immersion Passivation Method for High-K/Ge Stack Formation

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