The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary...
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The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.
This paper mainly discusses issues concerning the architecture of time divided closed loop accelerometer. For this particular architecture mathematical relationship between the external acceleration detected by sensor...
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This paper mainly discusses issues concerning the architecture of time divided closed loop accelerometer. For this particular architecture mathematical relationship between the external acceleration detected by sensor and the voltage output of the readout circuits is deduced. Both Matlab/Simulink model and Verilog-A model for such architecture are *** results agree with the mathematical *** circuits designed to work under 50kHz with feedback duty cycle ηbeing 60% are fabricated using 0.35μm HV CMOS *** results show a sensitivity of 1.518V/g.
The bias dependence of Channel Hot Carrier (CHC)degradation in 0.18μm SOI pMOSFETs is investigated in this *** classical bias modes (Vg@Isubmax and Vg=Vd)were applied to analyze the CHC degradation behavior of SOI **...
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ISBN:
(纸本)9781467324748
The bias dependence of Channel Hot Carrier (CHC)degradation in 0.18μm SOI pMOSFETs is investigated in this *** classical bias modes (Vg@Isubmax and Vg=Vd)were applied to analyze the CHC degradation behavior of SOI *** results show that at low Vg,hot carriers injection produced by impact ionization is the main factor contributed to ***,the degradation stressed at high Vg is controlled by both CHC and NBTI effect,showing the NBTI-like behavior at room temperature which indicates that NBTI effect is the dominant factor.A possible mechanism is put forward to explain the enhanced CHC degradation under Vg=Vd compared with pure NBTI *** influence of floating body on the performance degradation of PDSOI devices is also investigated.
This paper describes a radiation detection readout circuit for portable dosimeter which is aimed at low power,low noise and high counting rate.A current feedback baseline holder circuit is proposed to solve the baseli...
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This paper describes a radiation detection readout circuit for portable dosimeter which is aimed at low power,low noise and high counting rate.A current feedback baseline holder circuit is proposed to solve the baseline shift problem without any other performance *** core circuit has been implemented in 0.35μm CMOS *** achieves 46mV/fC conversion gain,200kcps counting rate and consumes 260μA current from 3.3V *** no detector is connected to the chip,the equivalent input noise charge is 0.094fC rms.
The effect of CHF3 gas flow rate on the trench shape and etch rate was studied for germanium-based device *** this study,a sidewall tilt angle larger than 80°with the trench depth of 300nm was achieved by optimiz...
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The effect of CHF3 gas flow rate on the trench shape and etch rate was studied for germanium-based device *** this study,a sidewall tilt angle larger than 80°with the trench depth of 300nm was achieved by optimizing the flow rate ratio of SF6/CHF3/He gas ***,based on the experimental results,a Linear Reactive Ion Etching(RIE) Model was proposed to predict the optimized composition of the SF6/CHF3/He gas mixture to obtain steep trenches with low etch rate,which may provide the guideline for the germanium etching process design.
Stress-induced degradation of STI-based LDMOSFETs has been studied by multi-region direct-current current voltage(MR-DCIV)spectroscopy, a new point of view over the traditional CP and Id-Vg characterization *** capabi...
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ISBN:
(纸本)9781467324748
Stress-induced degradation of STI-based LDMOSFETs has been studied by multi-region direct-current current voltage(MR-DCIV)spectroscopy, a new point of view over the traditional CP and Id-Vg characterization *** capability of identifying the interface states in LDMOSFETs has been demonstrated by MR-DCIV *** correlation between device degradation and MR-DCIV spectrum has been verified by 2D device simulation. Experimental results and the degradation mechanism for both ON-and OFF-state stresses have been addressed. The role played by the interface state at channel and STI region in LDMOSFETs has been clearly revealed through MR-DCIV *** term of the on-resistance,the OFF-state stress leads to the worst degradation in an STI-based nLDMOS,which is attributed to the interface state generation under STI region.
A readout integrated circuit for 384×288 uncooled infrared focal plane array (IRFPA) is presented in this paper. To overcome the kickback to sample and hold stage with less power consumption, a novel readout stag...
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A readout integrated circuit for 384×288 uncooled infrared focal plane array (IRFPA) is presented in this paper. To overcome the kickback to sample and hold stage with less power consumption, a novel readout stage of a Class AB op-amp with input stage in each column and sharing one cascode output stage is introduced. This IRFPA readout circuit has been designed and fabricated in 0.35um CMOS technology. The readout speed of the circuit can reach 7MHz, the dynamic range is 86.5dB and power consumption is 108mW. A 32×32 experimental chip has been verified by test results.
A phase interpolator(PI)-based clock data recovery(CDR)circuit for RapidIO application is presented,which avoids the coupled interference of *** the integration of a digital control cell,the complex and area consu...
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ISBN:
(纸本)9781467324748
A phase interpolator(PI)-based clock data recovery(CDR)circuit for RapidIO application is presented,which avoids the coupled interference of *** the integration of a digital control cell,the complex and area consumption has been reduced *** adaptive bandwidth PLL structure is adopted so that it can provide clocks of three frequencies while maintain a good jitter *** a 0.13um CMOS process,the circuit has a jitter of 11.2ps@3.125Gbps with a power consumption of 21.7mW under 1.2V,and the core circuit area is 0.16mm2.
Thermal performance of AlGaN/GaN HEMT is a critical issue during the design stage, since it significantly affect the lifetime of the device. This paper introduces a three-dimensional modeling technique including elect...
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Thermal performance of AlGaN/GaN HEMT is a critical issue during the design stage, since it significantly affect the lifetime of the device. This paper introduces a three-dimensional modeling technique including electro-thermal coupling effects for investing the thermal characteristic of the AlGaN/GaN HEMT. The method achieves a good balance between simulation time and accuracy through iterative calculation between the 2D and 3D model.
In this study, Ti/Al/Ni/Au Ohmic contact to AlGaN/GaN high electron mobility transistors was fabricated and demonstrated distribution of bright and dark areas on the surface. Surface element analyses show that it is o...
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In this study, Ti/Al/Ni/Au Ohmic contact to AlGaN/GaN high electron mobility transistors was fabricated and demonstrated distribution of bright and dark areas on the surface. Surface element analyses show that it is of great difference in the Ni and Au content between these two kinds of regions. According to transmission electron microscopy and corresponding Electron dispersive x-ray spectroscopy analyses, plenty of Ni was detected in dislocation rich regions while rare Ni was left in dislocation free regions so that Au tended to accumulate in the form of AlAu x binary alloy. The surface nonuniformity presented on the surface should be attributed to the nonuniform interfacial reactions resulted from the dislocations.
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