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International Electron devices Meeting (IEDM)

作者： Runsheng Wang Tao Yu Ru Huang Yujie Ai Shuangshuang Pu Zhihua Hao Jing Zhuge Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, the nanowire (NW) line-edge/width roughness (LER/LWR) effects in Si nanowire transistors (SNWTs) are investigated by both experiments and theoretical analysis. New LER/LWR characteristics are first observed in SNWTs, which exhibits suppressed randomization and enhanced systematic variation, rather than pure random LER/LWR in planar and FinFET devices. An improved characterization method is proposed to distinguish the random and systematic variation components in NW LER/LWR. For the first time, the effects of the key fabrication process on the NW LWR are studied in detail, including impacts of different oxidation temperature, NW channel orientations, and patterning techniques (hardmask trimming, spacer define and E-beam lithography). The results indicate that the spacer define method combined with self-limiting oxidation is beneficial for SNWTs. The mechanism of reducing the random variation in NW LER/LWR is analyzed, considering 2-D stress-retarded curvature-dependent oxidation. Taken into account the variation of quantum confined carrier profile, a physical device model is also developed, providing some guidelines for LER/LWR-hardening design of SNWTs.

关键词： Oxidation Systematics Correlation Silicon Degradation Temperature Temperature measurement

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Two Effective Single-Loop High-Performance Sigma-Delta Modulators Based on 0.13μm CMOS

Two Effective Single-Loop High-Performance Sigma-Delta Modul...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Hongyi Li Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After simulation, under the same circuit conditions, feedback structure gives better performance than feed-forward one. The experiment result could be a useful reference for the topology choice.

关键词： sigma-delta modulator switch-capacitor (SC) integrator feedback topology feed-forward topology high-resolution

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A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic linearity

A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic line...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Zhao Junlei Wang Yuan Zhao Zhihui Jia Song Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-μm CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.

关键词： Arrays Linearity Impedance Switches Encoding Systematics CMOS integrated circuits

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A clock and data recovery circuit for 3.125Gb/s RapidIO SerDes

A clock and data recovery circuit for 3.125Gb/s RapidIO SerD...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Zhao Zhihui Wang Yuan Zhao Junlei Yang Hailing Jia Song Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to lessen the problems in routing high speed clocks and reduce power. An improved half rate bang-bang phase detector is presented to assure the stability of the system. Moreover, the paper proposes a simplified control scheme for the phase interpolator to further reduce power and cost. The CDR takes an area of less than 0.05 m m 2 , and post simulation shows that the CDR has a RMS jitter of UI pp /32 (11.4 ps @3.125GBaud) and consumes 9.5 mW at 3.125 GBaud.

关键词： Bandwidth Clocks Jitter

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Cascade 2–2 sigma-delta modulators for wideband high-resolution applications

Cascade 2–2 sigma-delta modulators for wideband high-resolu...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Hongyi Li Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction Second, a flexible SMASH 2-2 has been proposed to choose appropriate coefficients for different requirements. Third, a SMASH 2-2 with feed-forward quantization noise self-coupled structure has been displayed to cancel quantization error of the preceding stage totally. Detailed simulation results and comparisons demonstrate the performance of these topologies.

关键词： Multi-stage noise shaping Modulation Quantization Topology Noise Digital filters Bandwidth

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Predictive Modeling of Capacitance and Resistance in Gate-all-around Cylindrical Nanowire MOSFETs for Parasitic Design Optimization

Predictive Modeling of Capacitance and Resistance in Gate-al...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Qiumin Xu Jibin Zou Jieyin Luo Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457977

This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Qside. Cof, Rsd RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.

关键词： Quantum capacitance Logic gates Delay Resistance Solid modeling Analytical models

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Study of LDMOS-SCR: A High Voltage ESD Protection Device

Study of LDMOS-SCR: A High Voltage ESD Protection Device

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Peng Zhang Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and... 详细信息

ISBN: (纸本)9781424457977

关键词： electrostatic discharge protection triggering voltage HEAT DISSIPATION High Voltage energy component LDMOS

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Impacts of Diameter-Dependent Annealing on S/D Extension Random Dopant Fluctuations in Silicon Nanowire MOSFETs

Impacts of Diameter-Dependent Annealing on S/D Extension Ran...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Tao Yu Runsheng Wang Wei Ding Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457977

In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSd variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSd dominates that of ON current. The tradeoff between RSd and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs.

关键词： Nanowire Diameter drive current digital differential analyzers bis(p-chlorophenyl)acetic acid annealing Silicon VOLTAGE Random

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Pulse Voltage Dependent Resistive Switching Behaviors of HfO2-Based RRAM

Pulse Voltage Dependent Resistive Switching Behaviors of HfO...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Bin Gao Bing Chen Yuansha Chen Lifeng Liu Xiaoyan Liu Ruqi Han Jinfeng Kang Institute of Microelectronics Peking University & Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Beijing 100871 China

Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can be improved. Voltage pulse controlled resistance states were observed. This behavior may provide the new application with the new function circuits.

关键词： Resistance Voltage control Switches Resistors Tin Process control

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A VCO sub-band selection circuit for fast PLL calibration

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Journal of Semiconductors 2009年第8期30卷 153-155页

作者：宋颖王源贾嵩赵宝瑛 Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

关键词： PLL VCO calibration

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