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A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technology

A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technol...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Le Ye Huailin Liao Fei Song Jiang Chen Huilin Xiao Ruiqiang Liu Junhua Liu Xinan Wang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper presents a UHF band (840 MHz~925 MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18 μm CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the transceiver. A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise corner. The transceiver, with an on-chip power-amplifier (PA) driver to drive off-chip PA, supports DSB-ASK, SSB-ASK and PR-ASK modulation schemes. A sigma-delta PLL is also implemented for 250 kHz channel hopping. Measurement results are given. Mixer achieves -8dBm P1 dB and 6.25 dB noise figure, phase noise of PLL is -127 dBc/Hz @ 1 MHz offset and settling time of channel hopping is within 30 μs. Settling time of killing leakage is less than 15 μs. The sensitivity of receiver can be -81dBm @ 40 kHz link frequency (LF). The total silicon area of the transceiver is 13 mm 2 , and draws 75 mA for 1.8 V supply voltage.

关键词： CMOS technology Radiofrequency identification Transceivers Phase locked loops Protocols ISO standards IEC standards CMOS process Transmitters Directional couplers

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An acquisition circuit in Global Positioning System receivers

An acquisition circuit in Global Positioning System receiver...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Xiaoxin Cui Chungan Peng Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855;9781424421862

The conventional matched filter structures are investigated in this paper. An acquisition circuit based on the polyphase form matched filter in Global Positioning System (GPS) receiver is provided. At the cost of less hardware resource, the significant advantage in the speed of synchronization is offered. For 32×128 polyphase form matched filter, the critical path delay approximately reduces 1/2, the sample frequency would be double.

关键词： circuits Global Positioning System Frequency synchronization Matched filters Signal generators Hardware Shift registers Delay Satellites Glands

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A CMOS TDI readout circuit for infrared focal plane array

A CMOS TDI readout circuit for infrared focal plane array

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhongjian Chen Wengao Lu Ju Tang Yacong Zhang Cao Junmin Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A new structure 288 × 4 CMOS time delay and integration (TDI) readout integrated circuit (ROIC) is presented in this paper. The TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact layout. An experimental chip has been designed and fabricated in 0.5 ¿m double-poly-three-metal CMOS technology. Bi-directional TDI, defective element deselection and two-gain option (1.015 pC/2.03 pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform IRFPA. The readout speed of each out can reach 5 MHz and the dynamic range is 75.6 dB.

关键词： Circuit testing Bidirectional control Detectors microelectronics Delay effects CMOS technology Systolic arrays Switches Timing Signal detection

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CMOS folding and interpolating ADC with a mixed-averaging distributed T/H circuit

CMOS folding and interpolating ADC with a mixed-averaging di...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.

关键词： Sampling methods Power dissipation Switches Circuit simulation CMOS technology Synchronization Interpolation Clocks CMOS analog integrated circuits microelectronics

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A new configuration scheme for delay test in non-simple LUT FPGA designs

A new configuration scheme for delay test in non-simple LUT ...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Botao Sun Jianhua Feng Teng Lin Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

With the increased use of FPGA in widespread applications, its¿ size and speed has been rapidly increased, so more and more problems associated with performance defects are emerging. Performance defects such as delay defects will not lead to a functional fault, but will limit the frequency of the system. Only Stuck-at testing has not been sufficient to guarantee the reliability and quality, so testing delay fault becomes necessary. In this paper, in order to improve the efficiency and coverage of delay test, we first select the most suitable delay fault model for FPGAs, which is a good simulation for the actual situation. At the same time we proposed a new configuration on the basis of this. This method takes full advantage of the FPGAs¿ reconfiguration feature. It not only omits complex test pattern generation, but also optimizes the BIST circuits to minimize the area cost, and reaches higher fault coverage. To verify the theory, we use Xilinx vertex4 devices on the experimental test, and achieved approving results.

关键词： Delay Testing Table lookup Field programmable gate arrays Circuit faults Frequency Circuit simulation Test pattern generators Built-in self-test Cost function

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A comprehensive study on Schottky barrier nanowire transistors (SB-NWTs): Principle, physical limits and parameter fluctuations

A comprehensive study on Schottky barrier nanowire transisto...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Liangliang Zhang Zhaoyi Kang Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855;9781424421862

P-type Schottky barrier nanowire transistors (p-SB-NWTs) are computational studied in this paper. We analyzed the working principle and physical limits on their performance in details. The impact of Schottky contact of SB-NWTs on the current drivability, gate control and RF performance are studied comparing with conventional silicon nanowire transistors (SNWTs). It is pointed out that the inferior performance of SB-NWTs can not be solved by changing the S/D or channel materials. On the other hand, small V t , F t and on-off ratio fluctuation caused by process variation on channel diameter are observed, which is an advantage of SB-NWTs.

关键词： Schottky barriers Fluctuations MOSFETs Silicon Tunneling Silicides Nanoscale devices microelectronics CMOS technology Contact resistance

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Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN heterostructures

Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN het...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhihua Dong Jinyan Wang Min Yu Yilong Hao C. P. Wen Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

To improve the performances of ohmic contacts for GaN devices, a novel multilayer Ti/Al-based metal scheme (Ti/Al/Ti/Al/Ti/Al/Ti/Al/Ni/Au) on undoped AlGaN/GaN heterostructures was employed. A contact with ¿c (specific contact resistance) of 8.74E-07 ¿·cm2, Rc of 0.22 ¿·mm was demonstrated. Ohmic contacts with the novel metal structure were measured with I-V, SEM, HRTEM to show their properties. The results showed that ohmic contacts with novel structures have better surface morphology and proposed thermal stability than those using conventional Ti/Al/Ni/Au metal scheme, therefore ohmic contacts with novel structures should be better candidates for high power and high frequency GaN devices.

关键词： Ohmic contacts Aluminum gallium nitride Gallium nitride Gold Nonhomogeneous media Contact resistance Electrical resistance measurement Surface morphology Surface resistance Thermal stability

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A novel linear histogram BIST for ADC

A novel linear histogram BIST for ADC

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jianguo Ren Jianhua Feng Hongfei Ye Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property, a space decomposition technique is proposed to reduce the testing time. By utilizing this technique, ADC¿s static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.

关键词： Histograms Built-in self-test Hardware microelectronics Laboratories Circuit testing Analytical models Parameter estimation Computational modeling Circuit faults

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The implementation methods of high speed FIR filter on FPGA

The implementation methods of high speed FIR filter on FPGA

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International Conference on Solid-State and Integrated Circuit Technology

作者： Ying Li Chungan Peng Dunshan Yu Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.

关键词： Finite impulse response filter Field programmable gate arrays Arithmetic Job shop scheduling Digital signal processing microelectronics Energy consumption Programmable logic arrays Circuit synthesis Table lookup

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Characteristics of sub-100nm ferroelectric field effect transistor with high-k buffer layer

Characteristics of sub-100nm ferroelectric field effect tran...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Rui Jin Yuncheng Song Min Ji Honghua Xu Jinfeng Kang Ruqi Han Xiaoyan Liu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424421855

The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100 nm ferroelectric field effect transistor (FeFET) with high-k material as the buffer layer. Different configurations of gate stack are simulated and analyzed. It is shown that the structure of double-layer buffer can improve the device performance efficiently. Some important issues for FeFET scaling down are also discussed in this paper.

关键词： Ferroelectric materials FETs High K dielectric materials High-K gate dielectrics Buffer layers Polarization Threshold voltage Circuit simulation Capacitors Semiconductor process modeling

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