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International Conference on Solid-State and Integrated Circuit Technology

作者： Hanzun Zhang Song Jia Jiancheng Yang Yuan Wang Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

In a SRAM array, the largest power consumer is pre-charging or voltage switching on bit-lines in read or write operations. The paper presents a bit-line charge cycling based read and write assist circuit for static random-access memory. With help of the assist circuit, the BLs charges wasted in conventional design is reused for BLs pre-charging in next period. The proposed array is simulated in SMIC 14nm FinFET process with a supply voltage of 0.8V. Simulation results show that a 23%-43% power reduction is achieved compared with conventional designs.

关键词： Random access memory Power demand Voltage control Transistors Timing Heating systems Circuit stability

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GeC film with high substitutional carbon concentration formed by ion implantation and solid phase epitaxy for strained Ge n-MOSFETs

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Science China(Information Sciences) 2018年第6期61卷 259-261页

作者： Bingxin ZHANG Xia AN Xiangyang HU Ming LI Xing ZHANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Ge is considered as a promising channel material to replace Si because of its high carrier mobility than Si and compatibility with conventional Si process[1–3].Strain engineering has been widely used in S... 详细信息

关键词： GeC film with high substitutional carbon concentration formed by ion implantation and solid phase epitaxy for strained Ge n-MOSF HRTEM SPE

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Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology

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Science China(Information Sciences) 2018年第10期61卷 285-287页

作者： Bingxin ZHANG Xia AN Pengqiang LIU Xiangyang HU Ming LI Xing ZHANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Ge has been considered as a very promising candidate as a channel material of MOSFET to extend Moore’s law beyond sub-7 nm node, due to its high and symmetric mobility, as well as the compatibility with conventional Si process [1, 2].In spite of higher carrier mobility than Si, there are still several challenges for Ge MOSFETs, such as low electrical concentration of n-type dopants and high electron Schottky barrier height, resulting in large source/drain (S/D) series resistance.

关键词： Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology NPP Ni

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Pruning random resistive memory for optimizing analogue AI

arXiv

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arXiv 2023年

作者： Li, Yi Wang, Songqi Zhao, Yaping Wang, Shaocong Zhang, Woyu He, Yangu Lin, Ning Cui, Binbin Chen, Xi Zhang, Shiming Jiang, Hao Lin, Peng Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Xu, Xiaoxin Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Frontier Institute of Chip and System Fudan University Shanghai200433 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong University of Chinese Academy of Sciences Beijing100049 China Institute of Mind The University of Hong Kong Hong Kong

The rapid advancement of artificial intelligence (AI) has been marked by the large language models exhibiting human-like intelligence. However, these models also present unprecedented challenges to energy consumption and environmental sustainability, which are exacerbated by the increasing number of users and the development of even larger models. One promising solution is to revisit analogue computing, a technique that predates digital computing and exploits emerging analogue electronic devices, such as resistive memory, which features in-memory computing, high scalability, and nonvolatility that addresses the von Neumann bottleneck, slowdown of Moore’s law, and volatile DRAM of conventional digital hardware. However, analogue computing still faces the same challenges as before: programming nonidealities and expensive programming due to the underlying devices physics. Therefore, leveraging the efficiency advantage while mitigating the programming disadvantage of analogue computing with resistive memory is a major open problem in AI hardware and electronics communities. Here, we report a universal solution, software-hardware co-design using structural plasticity-inspired edge pruning to optimize the topology of a randomly weighted analogue resistive memory neural network. Software-wise, the topology of a randomly weighted neural network is optimized by pruning connections rather than precisely tuning resistive memory weights. Hardware-wise, we reveal the physical origin of the programming stochasticity using transmission electron microscopy, which is leveraged for large-scale and low-cost implementation of an overparameterized random neural network containing high-performance sub-networks. We implemented the co-design on a 40nm 256K resistive memory macro, observing 17.3% and 19.9% accuracy improvements in image and audio classification on FashionMNIST and Spoken digits datasets, as well as 9.8% (2%) improvement in PR (ROC) in image segmentation on DRIVE datasets, r

关键词： Energy utilization

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Adaptive Random Number Generator Based on RRAM Intrinsic Fluctuation for Reinforcement Learning

Adaptive Random Number Generator Based on RRAM Intrinsic Flu...

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International Symposium on VLSI Technology, Systems and Applications

作者： Lin Bao Zongwei Wang Zhizhen Yu Yichen Fang Yuchao Yang Yimao Cai Ru Huang Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

ISBN: (数字)9781728142326

ISBN: (纸本)9781728142333

In this work, a novel random number generator with adjustable adaptability is demonstrated based on the intrinsic fluctuation of resistive random access memory (RRAM). Experimental data shows the standard deviation of resistance state has a negative dependence on compliance current (CC), thus an adaptive random number generator (ARNG) can be realized by controlling the CC in RRAM set process. Benchmarking results show that the RRAM based ARNG can achieve same performance compared with software ARNG in reinforcement learning process of zebra finch's singing pattern.

关键词： Resistance Learning (artificial intelligence) Fluctuations Generators Standards Software Random access memory

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Dynamic neural network with memristive CIM and CAM for 2D and 3D vision

arXiv

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arXiv 2024年

作者： Zhang, Yue Zhang, Woyu Wang, Shaocong Lin, Ning Yu, Yifei He, Yangu Wang, Bo Jiang, Hao Lin, Peng Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100049 China ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Institute of the Mind The University of Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100049 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China University of Chinese Academy of Sciences Beijing100049 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

The brain is dynamic, associative and efficient. It reconfigures by associating the inputs with past experiences, with fused memory and processing. In contrast, AI models are static, unable to associate inputs with past experiences, and run on digital computers with physically separated memory and processing. We propose a hardware-software co-design, a semantic memory-based dynamic neural network (DNN) using memristor. The network associates incoming data with the past experience stored as semantic vectors. The network and the semantic memory are physically implemented on noise-robust ternary memristor-based Computing-In-Memory (CIM) and Content-Addressable Memory (CAM) circuits, respectively. We validate our co-designs, using a 40nm memristor macro, on ResNet and PointNet++ for classifying images and 3D points from the MNIST and ModelNet datasets, which not only achieves accuracy on par with software but also a 48.1% and 15.9% reduction in computational budget. Moreover, it delivers a 77.6% and 93.3% reduction in energy consumption. © 2024, CC BY.

关键词： Memristors

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A Physical Current Model for Multi-Finger Gate Tunneling FET with Schottky Junction

A Physical Current Model for Multi-Finger Gate Tunneling FET...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yimei Li Jin Luo Qianqian Huang Xia An Le Ye Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China Peking University Information Technology Institute (Tianjin Binhai)

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

Compared with conventional tunneling field-effect transistor (TFET), a novel multi-finger gate tunneling FET with Schottky junction (mFSB-TFET) can effectively obtain the steeper subthreshold slope due to tunneling electric field coupling effect, the higher I on due to the introduced multi-finger gate and Schottky junction, while keeping the ultra-low I off simultaneously. To facilitate the circuit simulation by using this new device, in this paper, we establish a physical model of the channel surface potential in both gate handle region and gate finger region, and then further calculate the tunneling current by considering tunneling electric field coupling effect and the Schottky current by considering the equivalent barrier reduction respectively. The model results with different structure parameters agree well with the Sentautus TCAD simulation results, which shows the validity of this model.

关键词： Semiconductor device modeling Couplings Simulation Tunneling Logic gates Junctions Electric fields

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High-Speed Trace Detection DROIC for 15μm-Pitch Cryogenic Infrared FPAs

High-Speed Trace Detection DROIC for 15μm-Pitch Cryogenic I...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Yuze Niu Yajun Zhu Wengao Lu Zhaofeng Huang Yuting Gu Yacong Zhang Zhongjian Chen Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics Peking University China Peking University information technology institute (Tianjin Binhai) China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper introduces a digital readout integrated circuit (DROIC) for 320×256 target-tracking infrared focal plane arrays(IRFPAs). The circuit is based on a two-stage ADC, which implements 10-bit coarse quantization and 4-bit fine quantization, enabling high frame frequency trace detection. In addition, the locating and independent output of sensitive pixels are realized by a scanning function, which greatly reduces output frequency and power consumption. The proposed ROIC of 15μm pixel-pitch is fabricated using 55nm 1P6M CMOS process. The pixel circuit consumes 379nW. Frame frequency of the target-tracking mode is 1 kHz, the two-stage ADC has a nonlinearity of 0.06%.

关键词： Quantization (signal) Capacitors Array signal processing Power demand Imaging Detectors Integrated circuits

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A 187-pW 51-ppm/°C Self-Adjusting Voltage Reference Circuit

A 187-pW 51-ppm/°C Self-Adjusting Voltage Reference Circuit

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International Conference on Solid-State and Integrated Circuit Technology

作者： Mingwei ZhU Kaixuan Du Tianqiao Wu Changwu Song Le Ye Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking university Beijing China Information Technology Institute Peking University Tianjin Binhai China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

This paper proposed a novel pico-watt voltage reference (VR) circuit for the Internet of Things (IoT) applications. The core circuit consists of purely NMOS transistors operating in the sub-threshold region. This circuit contains a high-precision, high-power VR circuit (VRH) and a low-power, low-accuracy adjustable VR circuit (VRL). After initialization, the output voltage of VRL is adjusted based on the output voltage of VRH automatically. VRH is turned off to save energy when adjustment is completed. After waiting a period of time, VRH is turned on again to calibrate the output voltage of VRL. Thus, with self-adjusting topology, our proposed circuit achieves high accuracy and low power consumption. The output voltage is 168.5mV, while the power consumption is only 187pW and the temperature coefficient (TC) is 51 ppm/°C from -40°C to 85°C.

关键词： Voltage control Power demand MOS devices Very large scale integration Transistors Temperature control Voltage measurement

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A wearable wireless bio-medical front-end circuit for monitoring electrophysiological signals 3

A wearable wireless bio-medical front-end circuit for monito...

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3rd International Conference on Biological Information and Biomedical Engineering, BIBE 2019

作者： Yang, Zheng Wang, Jingmin Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China College of Career Technology Hebei Normal University Shijiazhuang China

ISBN: (纸本)9783800750269

An ECG readout front-end for long-term sleep monitoring is presented in this paper and features high common-mode rejection ratio (CMRR) and low input referred noise. The proposed front-end circuit composed of an AC coupled chopping instrumentation amplifier (CCIA), a SC-filter and a 10 bit SAR ADC. The proposed circuit, built in standard 0.18μm CMOS technology, consumes 1.6 μW from 0.5 V. According to the simulation, the AC coupled IA's CMRR is over 90 dB and input referred noise is merely l.28 μVrms. With the input impedance boost loop, a constant 2.4GO input impedance is achieved (@ typical condition). With the chip, for ECG sensor data, a QRS detection algorithm for heart beat rate calculation is implemented to demonstrate smartphone computation feasibility for real-time signal processing. © VDE VERLAG GMBH · Berlin · Offenbach.

关键词： Electrocardiograms

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