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Effects of Si δ-Doping Condition and Growth Interruption on Electrical Properties of InP-Based High Electron mobility Transistor Structures

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Chinese Physics Letters 2015年第9期32卷 112-115页

作者：周书星齐鸣艾立鹍徐安怀汪丽丹丁芃金智 State Key Laboratory of Functional Materials for lnformatics Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050 Microveave Devices and Integrated Circuits Department Key Laboratory of Microelectronics Device and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029

The InGaAs/InAIAs/InP high electron mobility transistor （HEM：F） structures with lattice-matched and pseudo- morphic channels are grown by gas source molecular beam epitaxy. Effects of Si ^-doping condition and growth interruption on the electrical properties are investigated by changing the Si-cell temperature, doping time and growth process. It is found that the optimal Si ^-doping concentration （Nd） is about 5.0 x 1012 cm-2 and the use of growth interruption has a dramatic effect on the improvement of electrical properties. The material structure and crystal interface are analyzed by secondary ion mass spectroscopy and high resolution transmission elec- tron microscopy. An InGaAs/InAiAs/InP HEMT device with a gate length of lOOnm is fabricated. The device presents good pinch-off characteristics and the kink-effect of the device is trifling. In addition, the device exhibits fT = 249 GHa and fmax 〉 400 GHz.

关键词： InP InGaAs Doping Condition and Growth Interruption on Electrical Properties of InP-Based High Electron mobility Transistor Structures Effects of Si

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Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization

Deep Insights into Dielectric Breakdown in Tunnel FETs with ...

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IEEE International Electron devices Meeting

作者： Qianqian Huang Rundong Jia Jiadi Zhu Zhu Lv Jiaxin Wang Cheng Chen Yang Zhao Runsheng Wang Weihai Bu Wenbo Wang Jin Kang Kelu Hua Hanming Wu Shaofeng Yu Yangyuan Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Semiconductor Manufacturing International Corporation (SMIC) Shanghai 201203 and Beijing 100176 China

ISBN: (纸本)9781509039036

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

关键词： Tunnel FETs Awareness Reliability

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New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications

New Insights into the Near-Threshold Design in Nanoscale Fin...

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IEEE International Electron devices Meeting

作者： Xiaobo Jiang Shaofeng Guo Runsheng Wang Yuan Wang Xingsheng Wang Binjie Cheng Asen Asenov Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Synopsys 11 Somerset place Glasgow G3 7JT U.K

ISBN: (纸本)9781509039036

Energy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge - variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data. Significant improvements are achieved in the following three aspects: (1) Our newly proposed predictive compact variability models in all-region are accurately calibrated with experimental data, using a simple characterization method;(2) A new efficient approach for logic design space optimization is proposed based on a set of elaborately selected subthreshold FoMs, and the impacts of variation on energy efficiency, delay variation and failure probability are thoroughly investigated;(3) The conventional gate sizing method is also ameliorated specifically for FinFET NTV design. Based on silicon data, the proposed methodology is then demonstrated under V~(dd)=199mV and V_(dd)=145mV, targeting energy-efficiency priority and V_(dd) priority scenarios, respectively. This work provides helpful guidelines for FinFET variation-aware near-threshold design.

关键词： New Insights into Near-Threshold Design FinFET

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A physics-based compact model for material- and operation-oriented switching behaviors of CBRAM

A physics-based compact model for material- and operation-or...

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International Electron devices Meeting (IEDM)

作者： Y. D. Zhao J. J. Hu P. Huang F. Yuan Y. Chai X. Y. Liu J. F. Kang Institute of Microelectronics Peking University Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Innovation Center for MicroNanoelectronics and Integrated System Beijing China Department of Applied Physics The Hong Kong Polytechnic University Hong Kong China

ISBN: (纸本)9781509039036

A physics-based compact model is developed to capture the essential resistive switching behaviors of conductive-bridge random access memory (CBRAM) under DC and AC operations. Three types of evolution modes of conductive filament correlated with material properties and operation schemes are modeled based on experimental observations. By modeling the temperature and electric-field effects as well as the electrical conduction, the model can well reproduce the DC and AC switching characteristics in different material stacks and operation modes. The calibrated model can be further implemented into SPICE to evaluate and optimize the array performance of CBRAM as a device-circuit-system co-design tool.

关键词： Mathematical model Switches Metals Oxidation Geometry Electric fields Data models

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A Leakage Tolerant True Single-Phase Clock Dual-Modulus Prescaler Scheme

A Leakage Tolerant True Single-Phase Clock Dual-Modulus Pres...

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Asia-Pacific Microwave Conference

作者： Song Jia Ziyi Wang Shilin Yan Yuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

ISBN: (纸本)9781479987689

A new leakage-tolerant true single-phase clock dual-modulus prescaler based on a stage-merged scheme is presented. Leakage-restricting transistors are used to reduce the leakage currents at critical nodes and leakage-related malfunctions are eliminated at minimal cost in terms of speed, power and area overheads. An HSPICE simulation in a 40 nm process shows that the proposed divide-by-2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable to the performance levels of referenced designs.

关键词： Leakage currents Transistors Performance evaluation Clocks Phase locked loops Robustness Frequency conversion

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Effect of annealing on the characteristics of Ti/Al ohmic contacts to p-Type 4H-SiC

Effect of annealing on the characteristics of Ti/Al ohmic co...

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European Conference on Silicon Carbide & Related Materials (ECSCRM)

作者： Yi-Dan Tang Hua-Jun Shen Xu-Fang Zhang Guo Fei Bai Yun Zhao-Yang Peng Xin-Yu Liu High-Frequency High-Voltage Device and Integrated Circuits R&D Center Institute of Microelectronics of Chinese Academy of Sciences Beijing China School of Physical Science and Technology Lanzhou University Lanzhou China State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of china Chengdu China

Ti/Al contacts deposited on p-type epilayer doped with Al at 2×10 19 cm -3 are reported. The current-voltage curves of Ti/Al contacts annealed at different temperatures from 800 to 1000 °C were measured, which provided the specific contact resistances (SCRs) of 6.59×10 -5 Ω/cm 2 and 7.81×10 -5 Ω/cm 2 after annealing at 900°C for 5min and 950°C for 2min, respectively. The microstructures of Ti/Al contact on P-type 4H-SiC were investigated by X-ray diffraction (XRD). The results of XRD show that the phases of Ti 3 SiC 2 was formed at the metal/SiC interface after annealing, which could be effective to ohmic contacts on P-type 4H-SiC. The quantitative phase analysis were also discussed, which show that the phase composition of Ti 3 SiC 2 is key factor for low resistance to P-type 4H-SiC. Moreover, simulations proved that the gradual Ti 3 SiC 2 ISL reduces or eliminates the effective barrier height at the metal/Ti 3 SiC 2 /p-type and may also contribute to low contact resistivity.

关键词： Ohmic contacts Silicon carbide Annealing X-ray scattering Temperature measurement Microstructure Metals

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Fabricating GeO_2 passivation layer by N_2O plasma oxidation for Ge NMOSFETs application

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Chinese Physics B 2014年第6期23卷 538-541页

作者：林猛安霞黎明云全新李敏李志强刘朋强张兴黄如 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 ***-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor （MOS） capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.

关键词： Ge GeO2 passivation N2O plasma oxidation Ge NMOSFETs

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Impacts of Dimensions, Number of Layers and Contact Structures on the Loss of Graphene-based Coplanar Waveguides through Simulations

Impacts of Dimensions, Number of Layers and Contact Structur...

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2015 IEEE 16th International Conference on Communication Technology(ICCT 2015)

作者： Qiaofeng Qin Zidong Wang Yuehui Jia Pei Peng Xin Gong Liming Ren Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

We present modeling and simulations of graphene coplanar waveguide(GCPW) under the frequency up to 50 GHz. Our simulation results show that the dimensions of GCPW greatly influence its insertion loss. In addition, different graphene layer numbers and structures of graphene-metal contact were also considered. We show that the usage of few-layer graphene and end-contact structure is able to decrease the insertion loss, which helps improve the radio-frequency performance of graphene coplanar waveguide.

关键词： Graphene coplanar waveguide Simulation Insertion loss Few-layer graphene Contact structure

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A high frequency resolution digitally controlled oscillator with differential tapped inductor

A high frequency resolution digitally controlled oscillator ...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Fan Yang Runhua Wang Xiaozhe Liu Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing Beijing CN

ISBN: (纸本)9781479983926

A novel architecture of high frequency resolution LC-tank based digitally controlled oscillator (DCO) is presented in this paper. The proposed architecture utilizes a differential tapped inductor and a capacitor array within the taps for fine frequency tuning. A prototype of 1.6 GHz DCO integrated in 0.18-μm CMOS technology exhibits a tuning range of 40.2% and a phase noise of -123.6 dBc/Hz@1MHz. With a minimal capacitance step of 7.5 fF, the frequency resolution is improved to 7.6 kHz/LSB. The DCO dissipates 3.2 mA from a 1.8 V supply and occupies an area of 0.46 mm 2 .

关键词： Inductors Capacitors Tuning Capacitance Arrays Phase noise

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A power efficient 1.0625–3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

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Science China(Information Sciences) 2014年第6期57卷 182-191页

作者： HOU ZhongYuan YANG Fan LIU JunHua ZHANG Xing Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel(FC),Peripheral Component Interconnect Express(PCIe),and RapidIO *** support multiple standards with a single low power and low cost design,the transceiver presented here uses a wide swing range source-series-terminated(SST)transmitter(TX),a passive receiver(RX)equalizer,a dual-loop phase locked loop(PLL)and a mixed signal clock and data recovery(CDR)*** proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter,and a passive equalizer that achieves 4 dB transmission in the *** dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR’s reference.A CDR with a phase interpolator(PI)is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 *** transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 *** supply voltages of 1.2 V and 3.3 V,the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at3.125 Gb/s.

关键词： serial transceiver multi-standard power efficiency SST CDR

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