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Selective Parallel CRC Computation Schemes for RapidIO

Selective Parallel CRC Computation Schemes for RapidIO

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Wu Fengfeng Jia Song Xu Heqing Wang Yuan Zhang Dacheng Key Laboratory of Microelectronics Devices and Circuits（MOE） Institute of Microelectronics Peking University

ISBN: (纸本)9781467324748

RapidIO is a high-performance standard for embedded *** to different ending alignments of RapidIO packets,the corresponding CRC computations should be *** this paper,two selective parallel computation schemes based on simplified intermediate value equations are *** with the reference designs,the power dissipations can be reduced by more than 30% meanwhile better balances between the speeds and resource consumptions can be achieved.

关键词： achieved speeds consumptions

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Clock Controlled Hybrid-latch flip-flops Design

Clock Controlled Hybrid-latch flip-flops Design

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Jia Song Yan Shilin Wu Fengfeng Wang Yuan Key Laboratory of Microelectronics Devices and Circuits(MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467324748

In order to obtain power efficient flip-flops,two novel Hybrid-latch schemes are introduced in this paper. They achieve high performance by shortening the critical data path and power efficiency by eliminating the inverter chain pulse *** simulation under SMIC 90nm process revealed that the two new flip-flop have excellent power and speed performance compared to the referenced *** can reduce 44.5% and 51.4% power dissipation,29.2% and 44.5% clock-to-output latency and 65.6% and 68.4% PDP.

关键词： simulation Hybrid Clock Controlled Hybrid-latch flip-flops Design PDP

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A multi-region trap characterization method and its reliability application on STI-based high-voltage LDMOSFETs

A multi-region trap characterization method and its reliabil...

引用

International Symposium on Power Semiconductor devices and Ics (ISPSD)

作者： Yandong He Ganggang Zhang Xing Zhang Institute of Microelectronics and Key Laboratory of Microelectronics Devices and Circuits Peking University Beijing China

The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

关键词： Stress Interface states Degradation Logic gates Substrates Voltage measurement

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Insights into Stress-Induced Degradation of STI-based LDMOSFETs by MR-DCIV spectroscopy

Insights into Stress-Induced Degradation of STI-based LDMOSF...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Yandong He Lin Han Ganggang Zhang Xing Zhang Congming Qi Wei Su Institute of Microelectronics and Key Laboratory of Microelectronics Devices and Circuits Peking University CSMC Technologies Corporation

ISBN: (纸本)9781467324748

Stress-induced degradation of STI-based LDMOSFETs has been studied by multi-region direct-current current voltage(MR-DCIV)spectroscopy, a new point of view over the traditional CP and Id-Vg characterization *** capability of identifying the interface states in LDMOSFETs has been demonstrated by MR-DCIV *** correlation between device degradation and MR-DCIV spectrum has been verified by 2D device simulation. Experimental results and the degradation mechanism for both ON-and OFF-state stresses have been addressed. The role played by the interface state at channel and STI region in LDMOSFETs has been clearly revealed through MR-DCIV *** term of the on-resistance,the OFF-state stress leads to the worst degradation in an STI-based nLDMOS,which is attributed to the interface state generation under STI region.

关键词： LDMOS STI Insights into Stress-Induced Degradation of STI-based LDMOSFETs by MR-DCIV spectroscopy

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Enhanced Nitrogen Plasma Immersion Passivation Method for High-K/Ge Stack Formation

Enhanced Nitrogen Plasma Immersion Passivation Method for Hi...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Meng Lin Quanxin Yun Min Li Zhiqiang Li Xia An Ming Li Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper,an enhanced Ge surface passivation method by nitrogen plasma immersion with adding RIE power is presented and experimentally demonstrated. With the acceleration effect resulting from electric field induced by proper RIE power,more nitrogen plasma will drift to Ge surface to passivate the dangling *** is shown that nitrogen plasma immersion with RIE power is efficient in suppressing Ge suboxide growth during high-K dielectric deposition,reducing interface states and improving the C-V characteristic of both p-MOS and n-MOS capacitors in terms of flat-band voltage and hysteresis.

关键词： MOS RIE Enhanced Nitrogen Plasma Immersion Passivation Method for High-K/Ge Stack Formation

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Investigation on Channel Hot Carrier Degradation of Ultra Deep Submicron SOI pMOSFETs

Investigation on Channel Hot Carrier Degradation of Ultra De...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Liang-Xi Huang Xia An Fei Tan Wei-Kang Wu Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467324748

The bias dependence of Channel Hot Carrier (CHC)degradation in 0.18μm SOI pMOSFETs is investigated in this *** classical bias modes (Vg@Isubmax and Vg=Vd)were applied to analyze the CHC degradation behavior of SOI *** results show that at low Vg,hot carriers injection produced by impact ionization is the main factor contributed to ***,the degradation stressed at high Vg is controlled by both CHC and NBTI effect,showing the NBTI-like behavior at room temperature which indicates that NBTI effect is the dominant factor.A possible mechanism is put forward to explain the enhanced CHC degradation under Vg=Vd compared with pure NBTI *** influence of floating body on the performance degradation of PDSOI devices is also investigated.

关键词： SOI CHC Investigation on Channel Hot Carrier Degradation of Ultra Deep Submicron SOI pMOSFETs

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A Radiation Detection Readout Circuit with Current Feedback Baseline Holder

A Radiation Detection Readout Circuit with Current Feedback ...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Xiao-Lu Chen Ya-Cong Zhang Wen-Gao Lu Zhong-Jian Chen Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

This paper describes a radiation detection readout circuit for portable dosimeter which is aimed at low power,low noise and high counting rate.A current feedback baseline holder circuit is proposed to solve the baseline shift problem without any other performance *** core circuit has been implemented in 0.35μm CMOS *** achieves 46mV/fC conversion gain,200kcps counting rate and consumes 260μA current from 3.3V *** no detector is connected to the chip,the equivalent input noise charge is 0.094fC rms.

关键词： A Radiation Detection Readout Circuit with Current Feedback Baseline Holder

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Reactive Ion Etching of Germanium Using SF6/CHF3/He gas mixture

Reactive Ion Etching of Germanium Using SF6/CHF3/He gas mixt...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Min Li Meng Lin Quanxin Yun Zhiqiang Li Xia An Ming Li Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The effect of CHF3 gas flow rate on the trench shape and etch rate was studied for germanium-based device *** this study,a sidewall tilt angle larger than 80°with the trench depth of 300nm was achieved by optimizing the flow rate ratio of SF6/CHF3/He gas ***,based on the experimental results,a Linear Reactive Ion Etching(RIE) Model was proposed to predict the optimized composition of the SF6/CHF3/He gas mixture to obtain steep trenches with low etch rate,which may provide the guideline for the germanium etching process design.

关键词： RIE Reactive Ion Etching of Germanium Using SF6/CHF3/He gas mixture CHF

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A Power Clamp Circuit Using Current Mirror for On-chip ESD Protection

A Power Clamp Circuit Using Current Mirror for On-chip ESD P...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Guangyi Lu Yuan Wang Xuelin Zhang Song Jia Ganggang Zhang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits(MoE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467324748

A power clamp circuit using current mirror is proposed in this *** current mirror is used for capacitance multiplication in the proposed circuit. Besides,the proposed circuit has different turn-on and turn-off paths towards clamp transistor and it employs a non-traditional phase inverter in the turn-on path of clamp *** results verify that the proposed circuit has enhanced ability to discharge static charges during an ESD event while making the ESD pulse detection CR time constant notably *** the reduction of CR time constant,the proposed circuit has better immunity to mis-triggering and is less chip area-consuming.

关键词： Electrostatic discharge(ESD),power clamp circuit,current mirror,mis-triggering

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Binary Tree Structure Random Dynamic Element Matching Technique in Current-Steering DACs

Binary Tree Structure Random Dynamic Element Matching Techni...

引用

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology(ICSICT-2012)

作者： Guangliang Guo Yuan Wang Wei Su Song Jia Ganggang Zhang Xing Zhang Key Laboratory of Microelectronics Devices and Circuits（MoB）Institute of Microelectronics Peking University

ISBN: (纸本)9781467324748

A novel Dynamic Element Matching（DEM）method is presented to improve the static and dynamic performance of Nyquist-rate current-steering digital to analog converter（DAC）.Compared to conventional DEM methods,this approach only increases or decreases the number of selected unit current sources randomly when the input code ***,signal dependent distortions can be eliminated efficiently at high sampling frequencies.A 6-bit current-steering DAC model adopting the proposed DEM coding method was built up to verify the performance in *** could reach a better SFDR（56dB）value and a better DNL（0.26LSB） and INL（0.45LSB）value compared with traditional DEM methods.

关键词： traditional method compared

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