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High-quality and large-grain epi-like Si film by NiSi2-seed initiated lateral epitaxial crystallization（SILEC）

Science China(Information Sciences) 2020年第12期63卷 272-274页

作者： Yuancheng YANG Baotong ZHANG Xiaoqiao DONG Xiaokang LI Shuang SUN Qifeng CAI Ran BI Xiaoyan XU Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Three-dimensional monolithic integration (3D-MI)has recently emerged for both "more Moore"and "more than Moore" applications, because of its high integration density, high bandwidth and multi-functions [1]. With 3D-MI, different types of devices can be stacked on the same platform and in a single process flow.

关键词： 3D monolithic integration (3D-MI) NiSi2-seed low-temperature crystallization epitaxial barrier layer metal contamination

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Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2Bi-Layer Dipole-First Process Using PVD Method for Advanced IC Technology

Experimental Investigation of Ultra-Low Temperature LA2O3/HF...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Wei, Yanzhao Yao, Jiaxin Xu, Renren Zhang, Qingzhu Yin, Huaxiang Chinese Academy of Sciences Integrated Circuit Advanced Process R&d Center Institute of Microelectronics Beijing100029 China Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronic Devices and Integrated Technology Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

ISBN: (纸本)9798350311006

In this paper, a La2O3/HfO2 bi-layer dipole-first (DF) process is proposed and investigated by ultra-low temperature PVD dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3D-IC (M3D) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (VFB) negatively shifts 60 mV with sub-1nm La2O3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (Dit) are suppressed by La2O3/HfO2 bi-layer DF process to improve device performance. These results exhibit a promising bi-layer DF process in low thermal integration for advanced IC technology. © 2023 IEEE.

关键词： Timing circuits

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Recent progress on fabrication and flat-band physics in 2D transition metal dichalcogenides moiré superlattices

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Journal of Semiconductors 2023年第1期44卷 43-55页

作者： Xinyu Huang Xu Han Yunyun Dai Xiaolong Xu Jiahao Yan Mengting Huang Pengfei Ding Decheng Zhang Hui Chen Vijay Laxmi Xu Wu Liwei Liu Yeliang Wang Yang Xu Yuan Huang Advanced Research Institute of Multidisciplinary Science Beijing Institute of TechnologyBeijing 100081China Beijing National Laboratory for Condensed Matter Physics Institute of PhysicsChinese Academy of SciencesBeijing 100190China School of Physical Sciences University of Chinese Academy of SciencesBeijing 100049China School of Integrated Circuits and Electronics MIIT Key Laboratory for Low-Dimensional Quantum Structure and DevicesBeijing Institute of TechnologyBeijing 100081China BIT Chongqing Institute of Microelectronics and Microsystems Chongqing 401332China

Moiré superlattices are formed when overlaying two materials with a slight mismatch in twist angle or lattice constant. They provide a novel platform for the study of strong electronic correlations and non-trivial band topology, where emergent phenomena such as correlated insulating states, unconventional superconductivity, and quantum anomalous Hall effect are discovered. In this review, we focus on the semiconducting transition metal dichalcogenides(TMDs) based moiré systems that host intriguing flat-band physics. We first review the exfoliation methods of two-dimensional materials and the fabrication technique of their moiré structures. Secondly, we overview the progress of the optically excited moiré excitons, which render the main discovery in the early experiments on TMD moiré systems. We then introduce the formation mechanism of flat bands and their potential in the quantum simulation of the Hubbard model with tunable doping, degeneracies, and correlation strength. Finally, we briefly discuss the challenges and future perspectives of this field.

关键词： flat-band physics two-dimensional materials moirésuperlattices Hubbard model moiréexcitons

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Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure

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Science China(Information Sciences) 2020年第4期63卷 245-247页

作者： Rundong JIA Liang CHEN Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Dear editor,Two-dimensional (2D) semiconductors have emerged as one of the most promising material candidates for next-generation electronic devices [1].Owing to the broad range of bandgap diversity and the pristine i... 详细信息

关键词： Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure VDS

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High-spatiotemporal-resolution chip analysis using a fiber-coupled quantum sensor based on diamond N-V centers

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Physical Review Applied 2025年第2期23卷 024050-024050页

作者： Youwei Liu Fazhan Zhao Jing Li Zhenfeng Li Lei Wang Bo Li Key Laboratory of Science and Technology on Silicon Devices Institute of Microelectronics Chinese Academy of Sciences 100029 Beijing China School of Integrated Circuits University of Chinese Academy of Sciences 101408 Beijing China Communication and Information Engineering Center Institute of Microelectronics Chinese Academy of Sciences 100029 Beijing China

We propose a chip analysis method using a fiber-optic quantum sensor based on diamond nitrogen-vacancy (N-V) centers to capture the magnetic field associated with short-pulse currents in chips. The fiber-coupled diamond N-V sensor was precisely positioned at the target region of the chip. We performed real-time monitoring of the N-V center fluorescence responses to pulsing magnetic fields generated by the pulse signals in the test chip through continuous-wave optically detected magnetic resonance. This allowed the accurate reconstruction of the chip internal node signal variations. We successfully achieved a time resolution of 200 ns, which was consistent with the metastable state lifetime of the N-V centers at room temperature. Furthermore, we evaluated the shot noise–limited magnetic sensitivity, which was found to be 6.3nT/Hz1/2. The proposed system exhibited swift responsivity to short pulse currents in the chip, providing highly accurate spatial localization of magnetic field variations. It satisfied the demand for rapid response and precise positioning in chip testing. Overall, this study validates the potential application of N-V centers in the domain of chip security analysis, offering a solution for chip diagnostics.

关键词： Quantum optics

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Modeling Non-Uniformity During Two-Step Dry Etching of Si/SiGe Stacks for Gate-All-Around FETs

Modeling Non-Uniformity During Two-Step Dry Etching of Si/Si...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Ziyi Hu Lado Filipovic Junjie Li Lingfei Wang Zhicheng Wu Rui Chen Yayi Wei Ling Li State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors Institute for Microelectronics TU Wien Vienna Austria

ISBN: (数字)9798331516352

ISBN: (纸本)9798331516369

Selective lateral etching of the SiGe layers is one of the most critical steps in Gate-All-Around Field-Effect Transistor (GAAFET) fabrication, which is the basis for the formation of an inner-spacer. Non-uniformity of substrate surface during wet or dry selective etching of SiGe is a common sight in industry, which cannot be modeled using standard process Technology Computer Aided Design (TCAD) approaches. In this paper, we propose a method for the continuous simulation of the two-step dry etching process - anisotropic etching of the Si/SiGe stack and subsequent isotropic selective etching of SiGe - to study the mechanism behind the non-uniform profile formation. The proposed method is able to simulate the non-uniform profile accurately, which was calibrated and verified with experimental data.

关键词： Industries Fabrication Design automation Dry etching Field effect transistors Logic gates Semiconductor process modeling Substrates Standards Silicon germanium

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Long-term and short-term plasticity independently mimicked in highly reliable Ru-doped Ge_(2)Sb_(2)Te_(5) electronic synapses

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InfoMat 2024年第8期6卷 85-96页

作者： Qiang Wang Yachuan Wang Yankun Wang Luyue Jiang Jinyan Zhao Zhitang Song Jinshun Bi Libo Zhao Zhuangde Jiang Jutta Schwarzkopf Shengli Wu Bin Zhang Wei Ren Sannian Song Gang Niu State Key Laboratory for Manufacturing Systems Engineering Electronic Materials Research LaboratoryKey Laboratory of the Ministry of Education&International Center for Dielectric ResearchSchool of Electronic Science and EngineeringXi'an Jiaotong UniversityXi'anthe People's Republic of China School of Integrated Circuits Peking UniversityBeijingthe People's Republic of China Beijing Microelectronics Technology Institute Beijingthe People's Republic of China National Key Laboratory of Human-Machine Hybrid Augmented Intelligence National Engineering Research Center for Visual information and Applicationsand School of SoftwareXi'an Jiaotong UniversityXi'anthe People's Republic of China State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Microsystem and Information TechnologyChinese Academy of SciencesShanghaithe People's Republic of China Key Laboratory of Microelectronics Device and Integrated Technology The Institute of Microelectronics of Chinese Academy of SciencesBeijingthe People's Republic of China University of Chinese Academy of Sciences Beijingthe People's Republic of China The State Key Laboratory for Manufacturing Systems Engineering&The International Joint Laboratory for Micro/Nano Manufacturing and Measurement Technology Xi'an Jiaotong UniversityXi'anthe People's Republic of China Leibniz-Institut für Kristallzüchtung Max-Born-Straße 2BerlinGermany Key Laboratory of Physical Electronics and Devices Ministry of EducationSchool of Electronic Science and EngineeringXi'an Jiaotong UniversityXi'anthe People's Republic of China The International Joint Laboratory for Micro/Nano Manufacturing and Measurement Technology Xi'an Jiaotong UniversityXi'anthe People's Republic of China

In order to fulfill the complex cognitive behaviors in neuromorphic systems with reduced peripheral circuits,the reliable electronic synapses mimicked by single device that achieves diverse long-term and short-term plasticity are *** change random access memory(PCRAM)is of great potential for artificial synapses,which faces,however,difficulty to realize short-term plasticity due to the long-lasting resistance *** work reports the ruthenium-doped Ge_(2)Sb_(2)Te_(5)(RuGST)based PCRAM,demonstrating a series of synaptic behaviors of short-term potentiation,pair-pulse facilitation,longterm depression,and short-term plasticity in the same single *** optimized RuGST electronic synapse with the high transformation temperature of hexagonal phase>380C,the outstanding endurance>108 cycles,the low resistance drift factor of 0.092,as well as the extremely high linearity with correlation coefficients of 0.999 and 0.976 in parts of potentiation and *** investigations also go insight to mechanisms of Ru doping according to thorough microstructure characterization,revealing that Ru dopant is able to enter GST lattices thus changing and stabilizing atomic arrangement of *** leads to the short-term plasticity realized by RuGST ***,the proposed RuGST electronic synapses performs a high accuracy of94.1%in a task of image recognition of CIFAR-100 database using ResNet *** work promotes the development of PCRAM platforms for large-scale neuromorphic systems.

关键词： electronic synapses neuromorphic computing PCRAM Ru-doped Ge_(2)Sb_(2)Te_(5)

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Design and fabrication of etchless lithium niobate photonic crystal nanobeam cavity for efficient photon manipulation 15

Design and fabrication of etchless lithium niobate photonic ...

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15th International Conference on Information Optics and Photonics, CIOP 2024

作者： Jiang, Zhi Yao, Danyang Gao, Yu Ran, Xu Wang, Jianguo Gan, Xuetao Liu, Yan Hao, Yue Han, Genquan State Key Laboratory of Wide-Bandgap Semiconductor Devices and Integrated Technology School of Microelectronics Faculty of integrated circuits Xidian University Xi’an710071 China Key Laboratory of Light Field Manipulation and Information Acquisition Ministry of Industry and Information Technology Shaanxi Key Laboratory of Optical Information Technology School of Physical Science and Technology Northwestern Polytechnical University Xi’an710129 China Hangzhou Institute of Technology Xidian University Hangzhou311200 China

ISBN: (数字)9781510686175

ISBN: (纸本)9781510686168

Recently, a novel approach that uses low-refractive-index polymers as loading materials coated on lithium niobate (LN) can dramatically simplify fabrication challenges for etching LN. On this platform, various devices operating in the transverse magnetic (TM) polarized state based on optical bound states in the continuum (BIC) have been demonstrated. However, in this configuration, the propagation loss of TM mode exhibits sensitivity to waveguide width, which limits design flexibility in waveguide structures. To this end, we designed transverse magnetic electric (TE) polarized photonic crystal structures with the same fabrication process using a y-cut LN on insulator (LNOI) substrate. The fabricated photonic crystal nanobeam cavity (PCNBC) achieves a Q factor over one order of magnitude higher than any previously reported PCNBCs on the etchless LNOI platform and retains a high transmission. To verify the strong photon manipulation ability, additional experiments such as thermo-optic tuning and optical bistability generation have been made. These results demonstrate the potential of our devices for efficient on-chip photon manipulation. © 2024 SPIE.

关键词： Optical bistability

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Study on the Anomalous Characteristics of Random Telegraph Noise in FeFETs

Study on the Anomalous Characteristics of Random Telegraph N...

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IEEE Silicon Nanoelectronics Workshop (SNW)

作者： Puyang Cai Yishan Wu Zixuan Sun Hao Li Xiaolei Wang Zhigang Ji Runsheng Wang Ru Huang School of Integrated Circuits Peking University Beijing China National Key Laboratory of Advanced Micro and Nano Manufacture Technology Shanghai Jiaotong University Shanghai China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences China Beijing

ISBN: (数字)9798350391633

ISBN: (纸本)9798350391640

In this work, we investigate the behavior of random telegraph noise (RTN) in HfO 2 -based FeFETs. Anomalously high location factors of RTN in FeFETs are observed for the first time, which can be successfully explained by the lateral domain wall motion, with the help of a dynamic 2-D phase-field simulation. This work reveals the unique characteristics of RTN in HfO 2 -based FeFETs and provides insight into the ferroelectric switching process.

关键词： Conferences Noise Dynamics Switches Hafnium oxide Silicon FeFETs

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First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip

First Demonstration of a Design Methodology for Highly Relia...

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Symposium on VLSI Technology

作者： Tiancheng Gong Lihua Xu Wei Wei Pengfei Jiang Peng Yuan Bowen Nie Yuanquan Huang Yuan Wang Yang Yang Jianfeng Gao Junfeng Li Jun Luo Lingfei Wang Jianguo Yang Qing Luo Ling Li Steve S. Chung Ming Liu State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Institute of Electronics National Yang Ming Chiao Tung University Taiwan

In achieving a reliable operation of FRAM arrays at high temperature (300K-400K), we provide an optimized operation design methodology considering the temperature effect on 128kb ITIC FRAM chip for the first time. Firstly, we found that the conventional voltage selection scheme in ITIC FRAM array is not applicable at high temperature since the P r value read by low voltage decreases at high temperature, leading to a poor yield. Then, the mechanism of P r degradation under high temperature is systematically investigated through material characterizations and electrical measurements. It was found that the increase of the internal electric field $(\mathrm{E}_{\mathrm{b}\mathrm{i}\mathrm{a}\mathrm{s}})$ caused by electron de-trapping mainly contributes to the P r degradation. Moreover, a KMC model considering $\mathrm{E}_{\mathrm{b}\mathrm{i}\mathrm{a}\mathrm{s}}$ is developed, and the optimum voltage, which can mitigate the temperature effect from 300K-400K, is predicted. This predicted voltage is finally validated on 128kb ITIC FeRAM chip, and excellent properties including non-volatile $(150^{\circ}\mathrm{C}\gt10^{6}\mathrm{s})$ and high endurance $(\gt10^{11})$ under the predicted voltage are also demonstrated.

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