In this paper, a novel design method has been proposed to realize feed-forward low-distortion unity STF sigma-delta modulators which are the critical blocks in multi-loop SMASH structure. Using the method, a timing-re...
详细信息
In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been pro...
详细信息
ISBN:
(纸本)9781424467372
In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction. Second, a flexible SMASH 2-2 has been proposed to choose appropriate coefficients for different requirements. Third, a SMASH 2-2 with feed-forward quantization noise self-coupled structure has been displayed to cancel quantization error of the preceding stage totally. Detailed simulation results and comparisons demonstrate the performance of these topologies.
This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zer...
详细信息
ISBN:
(纸本)9781424467372
This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-μm CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.
This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to ...
详细信息
A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and...
详细信息
Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can b...
详细信息
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic pr...
详细信息
A study of two major types of LDMOS-SCR electrostatic discharge protection devices for 60V SOI BCD technology is presented. The difference of the P-anode implant positions influences the triggering mechanism of the tw...
详细信息
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quas...
详细信息
RapidIO is an open standard that provides high-performance interconnect for chip-to-chip, board-to-board, and chassis-to-chassis communications. In this paper, we present an executable RapidIO interconnect in which an...
详细信息
RapidIO is an open standard that provides high-performance interconnect for chip-to-chip, board-to-board, and chassis-to-chassis communications. In this paper, we present an executable RapidIO interconnect in which an improved Buffer structure based on flow control is put forward. It helps to provide a smooth data flow, strong built-in error detection and error recovery mechanisms. It is tested to increase utilization and lower packet latency. And it can be applied to reliable and high speed embedded system communications.
暂无评论