A CMOS phase-locked loop（PLL） which synthesizes frequencies between 474 and S58 MHz in steps of lMHz and settles in less than 180μs is *** PLL can be implemented as a sub-circuit for a frequency synthesizer which s...
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A CMOS phase-locked loop（PLL） which synthesizes frequencies between 474 and S58 MHz in steps of lMHz and settles in less than 180μs is *** PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling,integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency calibration（AFC） of programmable dichotomizing coarse tuning technology is *** novel AFC structure uses pulses of 2~n times of the PFD's reference frequency for counting and *** multi-band voltage controlled oscillators,which cover 866 to 1468 MHz and 1282 to 1892 MHz separately,are implemented so as to reduce VCO output noise and power consumption by reducing VCO gain on each frequency turning curse.I/Q carriers are generated by VCO output divided by *** in 0.18-μm CMOS technology,the PLL achieves phase noise of less than - 132dBc/Hz at 1.45 MHz offset.
A 6-bit 200Msps Folding/Interpolating analog to digital converter(ADC) with a novel dynamic encoder based on Rom theory is *** Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit sync...
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A 6-bit 200Msps Folding/Interpolating analog to digital converter(ADC) with a novel dynamic encoder based on Rom theory is *** Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power *** in SMIC 0.35um digital CMOS process,the whole ADC consumes only 35mW at a 3.3V voltage supply.
Two novel structures for explicit-pulsed flip-flops are proposed in this *** charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures,and the short cir...
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Two novel structures for explicit-pulsed flip-flops are proposed in this *** charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures,and the short circuit power consumption is diminished by overcoming the race problem as *** results also indicate the new structures are ideal for high-speed and low-power digital design.
P-type Schottky barrier nanowire transistors （p-SB-NWTs） are computational studied in this paper. We analyzed the working principle and physical limits on their performance in *** impact of Schottky contact of SB-NW...
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P-type Schottky barrier nanowire transistors （p-SB-NWTs） are computational studied in this paper. We analyzed the working principle and physical limits on their performance in *** impact of Schottky contact of SB-NWTs on the current drivability,gate control and RF performance are studied comparing with conventional silicon nanowire transistors（SNWTs）.It is pointed out that the inferior performance of SB-NWTs can not be solved by changing the S/D or channel *** the other hand,small V_t,F_t and on-off ratio fluctuation caused by process variation on channel diameter are observed,which is an advantage of SB-NWTs.
The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configuration...
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The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configurations of gate stack are simulated and *** is shown that the structure of double-layer buffer can improve the device performance *** important issues for FeFET scaling down are also discussed in this paper.
This paper implements a sixteen-order high-speed Finite Impose Response(TTR) filter with four different popular methods:Conventional multiplications and additions;Full custom Distributed Arithmetic(DA) scheme;Add-and-...
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This paper implements a sixteen-order high-speed Finite Impose Response(TTR) filter with four different popular methods:Conventional multiplications and additions;Full custom Distributed Arithmetic(DA) scheme;Add-and-Shift method with advanced calculation *** scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical *** of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed *** premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3%versus the largest conventional parallel multiplication implementation.
A low power Read-Out Integrated Circuit(ROIC) for a short-wave Infra-Red Focal Plane Array(IRFPA) is designed as a prototype for 1024×1024 image *** integration and readout scheme as well as highly efficient powe...
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A low power Read-Out Integrated Circuit(ROIC) for a short-wave Infra-Red Focal Plane Array(IRFPA) is designed as a prototype for 1024×1024 image *** integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme,novel low input capacitance column amplifier is *** Data rate is about 10M/s per channel,with a total power dissipation of 56mW.
This paper proposes a novel histogram BIST scheme for ADC static *** a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input *** on this property,a space decomposition tech...
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This paper proposes a novel histogram BIST scheme for ADC static *** a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input *** on this property,a space decomposition technique is proposed to reduce the testing *** utilizing this technique,ADC's static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.
A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented.A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique(PCEA) and opamp sh...
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A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented.A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique(PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and *** offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock *** with 0.5um CMOS technology,the ADC dissipates 65mw from a 5V supply,and achieves a peak SNDR of 70.1dB with a 1MHz full-scale sine input at 20MS/s.
In this paper,we have focused our attention on DC characteristics degradation of 0.18μm MOSFETs after 10-MeV proton *** is shown that the threshold voltage shift,the transconductance degradation and the saturation dr...
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In this paper,we have focused our attention on DC characteristics degradation of 0.18μm MOSFETs after 10-MeV proton *** is shown that the threshold voltage shift,the transconductance degradation and the saturation drain current decrease are lager in PMOSFETs,while small effects are exhibited in *** the analysis,it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the *** origin of the observed changes is due to the damage in spacer oxides of the *** mechanism involved is that the energetic protons incident on the spacer region lose their energy to displace the atoms, give rise to many defects,and create a disordered region(displacement damage region),where many defects and traps can capture positive charges to make the static characteristics ***,it is pointed out that the sidewalls are one of sensitive regions for irradiation hardness.
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