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A 900MHz UHF RFID Reader Transceiver in 0.18μm CMOS Technology

A 900MHz UHF RFID Reader Transceiver in 0.18μm CMOS Technol...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Le Ye Huailin Liao Fei Song Jiang Chen Huilin Xiao Ruiqiang Liu Junhua Liu Xinan Wang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

This paper presents a UHF band（840MHz25MHz） RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC *** architecture and modules for the proposed transceiver are described and implemented in a standard 0.18μm CMOS process. To suppress the leakage signal from transmitter to receiver,directional coupler and leakage cancellation circuit are introduced in the transceiver.A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise *** transceiver,with an on-chip Power-amplifier（PA） driver to drive off-chip PA,supports DSB-ASK,SSB-ASK and PR-ASK modulation schemes.A sigma-delta PLL is also implemented for 250kHz channel *** results are *** achieves -8dBm P1dB and 6.25dB noise figure,phase noise of PLL is -127dBc/Hz @1MHz offset and settling time of channel hopping is within 30μ*** time of killing leakage is less than 15μ*** sensitivity of receiver can be -81dBm@40 kHz link frequency（LF）.The total silicon area of the transceiver is 13mnr,and draws 75mA for 1.8V supply voltage.

关键词： A 900MHz UHF RFID Reader Transceiver in 0.18 m CMOS Technology Reader

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Efficient Encoding Scheme for Folding ADC

Efficient Encoding Scheme for Folding ADC

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

＜正＞An efficient encoding scheme is proposed for folding *** the encoder,XOR-OR encoding algoriflim and dynamic domino circuit are adopted.A novel method for wide-range error correction and bit synchronization is **... 详细信息

关键词： [IEEE keyword]Computed tomography Fault currents Heuristic algorithms Power dissipation Error correction Encoding Synchronization

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CMOS Folding and Interpolating ADC with a Mixed-Averaging Distributed T/H Circuit

CMOS Folding and Interpolating ADC with a Mixed-Averaging Di...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

＜正＞An 8-bit 200MHz low-power CMOS folding and interpolating analog-to-digital converter is presented.A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. the DNL/INL is 0.3/0.2LSB according to MATLAB simulation *** ADC is implemented in 0.5um CMOS technology and the total power dissipation is merely 96mW at a sampling rate of 200MHz.

关键词： [IEEE keyword]CMOS technology Synchronization Simulation Clocks CMOS integrated circuits Power dissipation Interpolation

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Bipolar Resistive Switching Behaviors of Ag/Si3N4/Pt Memory Device

Bipolar Resistive Switching Behaviors of Ag/Si3N4/Pt Memory ...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： B.Sun L.F Liu Y.Wang D.D.Han X.Y Liu R.Q.Han J.F.Kang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The resistive switching behavior of Ag/SiN/Pt device was observed and studied for the first time. Resistance ratio larger than 410～2 and 10～4s retention time were achieved which indicating its potential for resistive switching memory application.A physical model is proposed to explain the resistive switching behaviors of Ag/SiN/Pt devices.

关键词： LRS HRS Bipolar Resistive Switching Behaviors of Ag/Si3N4/Pt Memory Device

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A CMOS TDI Readout Circuit for Infrared Focal Plane Array

A CMOS TDI Readout Circuit for Infrared Focal Plane Array

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Zhongjian Chen Wengao Lu Ju Tang Yacong Zhang Cao Junmin Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

A new structure 288x4 CMOS time delay and integration(TDI) readout integrated circuit(ROIC) is presented in this *** TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact *** experimental chip has been designed and fabricated in 0.5μm double-poly-three-metal CMOS ***-directional TDI,defective element deselection and two-gain option(1.015pC/2.03pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform *** readout speed of each out can reach 5MHz and the dynamic range is 75.6dB.

关键词： TDI A CMOS TDI Readout Circuit for Infrared Focal Plane Array

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A Simple Nano-Scale Patterning Technology for FinFET Fabrication

A Simple Nano-Scale Patterning Technology for FinFET Fabrica...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Xu Han Chengen Yang Dingyu Li Shengdong Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper,a simple low-cost sub-50 nm silicon fin patterning technology is proposed and experimentally *** technology is based on a micro-meter level lithography equipment,that is,it does not need any critical photolithographic *** masking layer for fin formation is the nitride caped oxide layer which is reduced in width from sub-micrometer scale to nano-meter scale through a lateral etching in *** etching rate is shown to slow down as the etching process goes on.A nano-scale oxide hard mask can be achieved after the nitride is *** the cross-sectional view and top view of the etching process are shown by SEM *** indicate the simple patterning way is of low cost and under good control,and applicable to FinFET technology.

关键词： FinFET A Simple Nano-Scale Patterning Technology for FinFET Fabrication

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Impact Factors on the Performance of Schottky Barrier MOSFETs with Asymmetric Barrier Height at Source/Drain

Impact Factors on the Performance of Schottky Barrier MOSFET...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Du Xiong-Xiong Sun Lei Liu Xiao-Yan Han Ru-Qi Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/drain (A-SBFET) was numerically *** impact factors on the performance are *** results suggest the on-state characteristics of the devices are mainly determined by the source-side barrier height (SBH).Increasing SBH or decreasing body thickness can optimize the sub-threshold slope,and decreasing SBH can enhance the on-state current.

关键词： Impact Factors on the Performance of Schottky Barrier MOSFETs with Asymmetric Barrier Height at Source/Drain

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Fabrication and Characteristics of ZnO-based Thin Film Transistors

Fabrication and Characteristics of ZnO-based Thin Film Trans...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Dedong Han Yi Wang Shengdong Zhang Lei Sun Jinfeng Kang Xiaoyan Liu Gang Du Lifeng Liu Ruqi Han Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ZnO-based thin-film transistors(TFT) have been fabricated on p-Si(100) substrates by radio frequency(rf) magnetron sputtering at room temperature with a bottom gate *** XRD and SEM show that ZnO films had high crystalline *** ZnO films present an average optical transmission(including the glass substrate) of 80%in the visible part of the spectrum. The electrical properties of ZnO-based TFTs were investigated by I-V and I-V *** ZnO TFT operates in the enhancement mode with a channel mobility of 6.86 cm/V ? *** combination of transparency,high channel mobility and room temperature processing makes the ZnO-TFT a very promising low cost optoelectronic device for the next generation of flat panel display(FDP).

关键词： [IEEE keyword]Temperature measurement Sputtering X-ray scattering Films Substrates Thin film transistors Zinc oxide

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Design and Test Results of a Front-end ASIC for Radiation Detectors

Design and Test Results of a Front-end ASIC for Radiation De...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Zhang Yacong Chen Zhongjian Lu Wengao Ji Lijiu Zhao Baoying Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

A front-end ASIC for semiconductor radiation detectors is *** is composed of a Charge Sensitive Amplifier(CSA),a pulse shaper,and a Peak Detect and Hold(PDH) ***-resistor is used as source degeneration component to reduce the noise of current source in the *** ASIC has been designed in a 0.5um CMOS DPTM technology and tested with Verigy *** gain(PDH excluded) is 78.5mV/fC and the Equivalent Noise Charge(ENC) with detector disconnected is *** power dissipation without the output buffer is about 2.6mW.

关键词： CSA Design and Test Results of a Front-end ASIC for Radiation Detectors

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A New Configuration Scheme for Delay Test in Non-simple LUT FPGA Designs

A New Configuration Scheme for Delay Test in Non-simple LUT ...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Botao Sun Jianhua Feng Teng Lin Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

With the increased use of FPGA in widespread applications,its' size and speed has been rapidly increased,so more and more problems associated with performance defects are *** defects such as delay defects will not lead to a functional fault, but will limit the frequency of the *** Stuck-at testing has not been sufficient to guarantee the reliability and quality,so testing delay fault becomes *** this paper,in order to improve the efficiency and coverage of delay test,we first select the most suitable delay fault model for FPGAs,which is a good simulation for the actual *** the same time we proposed a new configuration on the basis of *** method takes full advantage of the FPGAs' reconfiguration *** not only omits complex test pattern generation,but also optimizes the BIST circuits to minimize the area cost, and reaches higher fault *** verify the theory, we use Xilinx vertex4 devices on the experimental test, and achieved approving results.

关键词： FPGA configuration delay-test LUT MUX

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