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2021 China Semiconductor Technology International Conference, CSTIC 2021

作者： Qin, Yabo Wang, Zongwei Chen, Qingyu Ling, Yaotian Wu, Lindong Cai, Yimao Huang, Ru Institute of Microelectronics Peking University Beijing100871 China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing100871 China

ISBN: (纸本)9781665449458

In this work, the influence of localized metal ion doping on the uniformity and analog behavior in TaOx-based RRAM is investigated. Experimental results show that Al ion local doping can improve the uniformity. The distributions of set/reset voltage and LRS/HRS become tighter. Moreover, the TaOx-based RRAM with Al doping shows excellent analog switching behaviors compared with the device without doping. The underlying mechanism may be explained by the reduced formation energy of oxygen vacancies and relayed traps in the doped area, which makes it easier to form incremental conductive filaments in the regions with high ion doping concentration. © 2021 IEEE.

关键词： RRAM

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Investigation of Electrical Characteristics on Morphotropic Phase Boundary of Hf1-xZrxO2 for Dynamic Random Access Memories

Investigation of Electrical Characteristics on Morphotropic ...

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China Semiconductor Technology International Conference (CSTIC)

作者： Kun Zhong Huaxiang Yin Zhaohao Zhang Fan Zhang Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China Xidian University Key Laboratory of Wide Bandgap Semiconductor Materials

This paper investigates the properties of different Zr compositions in $\mathrm{H}\mathrm{f}_{1-\mathrm{x}}\mathrm{Z}\mathrm{r}_{\mathrm{x}}\mathrm{O}_{2}$ films. Due to the morphotropic phase boundary (MPB) between the orthorhombic ferroelectric phase and the tetragonal anti-ferroelectric phase, a maximum $\kappa$ value of 55 was obtained for 9 nm $\mathrm{H}\mathrm{f}_{0.4}\mathrm{Z}\mathrm{r}_{0.6}\mathrm{O}_{2}$ films. Furthermore, the sufficiently low leakage current of the capacitors was confirmed. Finally, a promising switching endurance of up to $5\times 10^{9}$ cycles was also performed, which becomes one of the driving forces for next-generation dynamic random access memories (DRAM) cell capacitor dielectric materials.

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Effective gate length model for asymmetrical gate-all-around silicon nanowire transistors

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Science China(Information Sciences) 2020年第10期63卷 288-290页

作者： Xiaoqiao DONG Ming LI Wanrong ZHANG Yuancheng YANG Gong CHEN Shuang SUN Jianing WANG Xiaoyan XU Xia AN Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Faculty of Information Technology Beijing University of Technology

Dear editor,With the development of VLSI technology,gateall-around (GAA) silicon nano wire transistor(SNWT) has emerged as one of the most potential candidates for ultimately scaled CMOS devices at the end of the technology *** pioneering research studies have demonstrated super scalability and high performance with GAA SNWT [1-3].Whereas,in the practical fabrica-

关键词： gate-all-around nanowire effective gate length effective model asymmetrical

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Influence of Back Gate Bias on the Hot Carrier Reliability of DSOI nMOSFET

Influence of Back Gate Bias on the Hot Carrier Reliability o...

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Annual International Symposium on Reliability Physics

作者： Xinyi Zhang Kewei Wang Fang Wang Jiangjiang Li Zhicheng Wu Duoli Li Bo Li Jianhui Bu Zhengsheng Han Institute of Microelectronics of Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of Sciences Beijing China State key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

The hot carrier reliability under different back-gate bias in DSOI nMOSFET is studied. Reverse back-gate bias results in an over-all larger time exponents than the forward back-gate bias, which is attributed to the increased lateral electric field (as supported by TCAD simulation) and consequently a stronger interface state generation (related to SVE mechanisms). Such strong time acceleration is crucial for long term reliability prediction under circuit operation. The abnormal deviation among threshold voltage shift, linear/saturation drain current degradation is observed: through careful inspection of the degradation of the I- V characteristics, the competing role of the interface state generation and hot hole trapping is revealed, with a virtual channel shortening effect as supported by the increased DIBL values.

关键词： Degradation Simulation Hot carriers MOSFET circuits Logic gates Threshold voltage Interface states

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A Fully BEOL-Compatible (300°C Annealing) IGZO FeFET with Ultra-High Memory Window (10V) and Prominent Endurance (109)

A Fully BEOL-Compatible (300°C Annealing) IGZO FeFET with U...

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International Electron devices Meeting (IEDM)

作者： Pan Xu Pengfei Jiang Yang Yang Xueyang Peng Wei Wei Tiancheng Gong Yuan Wang Xiao Long Jiebin Niu Zhongguang Xu Chenxin Zhu Zhenhua Wu Qing Luo Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China University of Science and Technology of China Hefei Anhui China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

HfO 2 -based FeFET paves the way for the next generation NVM thecnology, however, demands for high memory window (MW) and roubust reliability (especially the endurance) cannot be combined in the current reported devices, and the contradiction of high MW and low thermal budget (aiming for BEOL compatibility) also needs to be solved. In this work, we propose an integrated ferroelectric (FE) Hf 0.5 Zr 0.5 O 2 (HZO) and amorphous In-Ga-Zn-O (a-IGZO) channel FeFET with a maximum 10V MW and prominent endurance up to 10 9 . Workfunction (WF) engineering is utilized to regualte the intrinsic $\mathrm{V}_{\mathrm{t}}$ to improve the PGM/ERS efficiency with full-loop polarization switching, and the adopted Mo gate can effectively reduce the thermal budget to 300°C ensuring a fully BEOL compatibility. Then with O 3 -plasma treatment to the gate electrode, the introduced tunneling layer can futher improve the MW by gate charge injection. The demonstrated FeFET shows great 3-bit/cell storage ability without states overlapping, high $\mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}}$ ratio $(>10^{7})$ , as well as great linearity and high $\mathrm{G}_{\max}/\mathrm{G}_{\min}$ (286) during synaptic weight modulation.

关键词： Performance evaluation Nonvolatile memory Thermal engineering Modulation Switches Logic gates Tunneling Reliability FeFETs Next generation networking

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A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Thickness (sub-8nm), Low Thermal Budget (350oC), 100% Initial Chip Yield, Low Power Consumption (0.7 pJ/bit at 2V write voltage), and Prominent Endurance (>1012)

A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Th...

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International Electron devices Meeting (IEDM)

作者： Pengfei Jiang Haijun Jiang Yang Yang Lu Tai Wei Wei Tiancheng Gong Yuan Wang Pan Xu Shuxian Lv Boping Wang Jianfeng Gao Junfeng Li Jun Luo Jianguo Yang Qing Luo Ming Liu State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Zhangjiang Lab Shanghai China School of Information Science and Engineering Shandong University Qingdao China

In this work, we successfully resolve the remanent polarization (P r ) degradation issue, which is caused by the thermal budget decreasing and the film thickness scaling of Hf 0.5 Zr 0.5 O 2 (HZO), and co-integrate the TiN/HZO/TiN capacitors with large initial P r and low operating voltage in the Back-End-of -Line (BEOL) of 130nm CMOS technology to provide a 256 Kbit 1T1C FeRAM chip. Firstly, we prove that the P r degradation is caused by the increasing component of anti-ferroelectric (AFE) phase. Then, utilizing the pre-crystallization engineering and O 3 treatment to the TiN bottom electrode (BE), not only the formation of t-phase is effectively suppressed, but also the required annealing temperature is reduced. The enhancement of ferroelectricity is related to the small thermal expansion of TiO 2 interface layer, which can induce large tensile stress to HZO during the annealing process. Moreover, the oxidization of TiN BE can prevent it absorbing oxygen from HZO, and the reduced oxygen vacancy (Vo) defects can improve both the retention and TDDB characteristics. Based on the above optimizations, the chip demonstrates 100% initial chip yield, >150mV sense margin after 10 12 write cycles, power consumption of 0.7 pJ/bit at 2V write voltage, over 10 12 endurance and 10 years retention.

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High-Speed, Low-Voltage, Small-Pitch and Robust Otft-Based Integrated Gate Driver for Active-Matrix Displays

SSRN

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SSRN 2023年

作者： Wu, Wanming Geng, Di Chen, Chuanke Chuai, Xichen Li, Shuai Lu, Nianduan Li, Ling State key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China

We design and fabricate a high-speed, low-voltage, small-pitch and robust integrated gate driver with organic thin-film transistors (OTFTs). The dual-gate OTFT devices have a field effect mobility of 0.78cm2/Vs, and on/off current ratio of above 108. A single stage of the gate driver consists of ten TFTs and two capacitors, with small pitch of 244μm. The fabricated circuit can output minimum pulse width of 5μs, which is compatible to full-high definition (FHD, 1,920×1,080) active-matrix displays with 60Hz frame rate. It can work at input swing of as low as 10V, with VGH2, VGH1 and VGL of 5V, 0V and -10V respectively. With the threshold voltage shift under positive and negative bias stress, the driver shows output signals without significant degradation and demonstrates its high reliability through simulation. © 2023, The Authors. All rights reserved.

关键词： Thin film transistors

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A novel tunnel FET design through hybrid modulation with optimized subthreshold characteristics and high drive capability

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Science China(Information Sciences) 2020年第2期63卷 245-247页

作者： Yang ZHAO Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University National Key Laboratory of Science and Technology on Micro/Nano Fabrication Peking University

Dear editor,As CMOS technology scaling down, the reduction of supply voltage and power consumption becomes extremely difficult due to the subthreshold swing(SS) limitation (60 m V/dec) at room *** FET (TFET) with band-to-band tunneling (BTBT) mechanism is regarded as one of the most promising emerging low-power devices due to its sub-60 m V/dec SS and ultra-low off-current

关键词： A novel tunnel FET design through hybrid modulation with optimized subthreshold characteristics and high drive capability FET

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Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction

Experimental Demonstration of A CT-FeFET Array with Intrinsi...

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International Electron devices Meeting (IEDM)

作者： Chao Li Jie Yu Xumeng Zhang Zhaohao Zhang Fangduo Zhu Siyuan Ouyang Pei Chen Lingli Cheng Gaobo Xu Qingzhu Zhang Huaxiang Yin Qi Liu Ming Liu State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000x and 4x improvements than GPU in power consumption and memory overhead.

关键词： Performance evaluation Power demand Neuromorphics Memory management Graphics processing units Trajectory Vehicle dynamics Synapses Long short term memory FeFETs

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Microscopic mechanism of imprint in hafnium oxide-based ferroelectrics

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Nano Research 2022年第4期15卷 3667-3674页

作者： Peng Yuan Ge-Qi Mao Yan Cheng Kan-Hao Xue Yunzhe Zheng Yang Yang Pengfei Jiang Yannan Xu Yuan Wang Yuhao Wang Yaxin Ding Yuting Chen Zhiwei Dang Lu Tai Tiancheng Gong Qing Luo Xiangshui Miao Qi Liu Key Laboratory of Microelectronic Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesNo.3Beitucheng West RoadBeijing 100029China University of Chinese Academy of Sciences 19 Yuquan RoadBeijing 100049China School of Integrated Circuits School of Optical and Electronic InformationHuazhong University of Science and Technology1037 Luoyu RoadWuhan 430074China Key Laboratory of Polar Materials and Devices(MOE) Department of ElectronicsEast China Normal University100 Guilin RoadShanghai 430079China Department of Mathematics and Theories Peng Cheng LaboratoryNo.2Xingke 1st StreetShenzhen 518055China

Hafnia-based ferroelectrics have greatly revived the field of ferroelectric memory(FeRAM),but certain reliability issues must be satisfactorily resolved before they can be widely applied in commercial *** particular,the imprint phenomenon severely jeopardizes the read-out reliability in hafnia-based ferroelectric capacitors,but its origin remains unclear,which hinders the development of its recovery *** this work,we have systematically investigated the imprint mechanism in TiN/Hf_(0.5)Zr_(0.5)O_(2)(HZO)/TiN ferroelectric capacitors using experiments and first-principles *** is shown that carrier injection-induced charged oxygen vacancies are at the heart of imprint in HZO,where other mechanisms such as domain pinning and dead layer are less *** imprint model based on electron de-trapping from oxygen vacancy sites has been proposed that can satisfactorily explain several experimental facts such as the strong asymmetric imprint,leakage current variation,and so *** on this model,an effective imprint recovery method has been proposed,which utilizes unipolar rather than bipolar voltage *** remarkable recovery performances demonstrate the prospect of improved device reliability in hafnia-based FeRAM devices.

关键词： hafnia-based ferroelectric imprint build-in electric field oxygen vacancy recovery

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