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2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Li, Chao Yu, Jie Zhang, Xumeng Zhang, Zhaohao Zhu, Fangduo Ouyang, Siyuan Chen, Pei Cheng, Lingli Xu, Gaobo Zhang, Qingzhu Yin, Huaxiang Liu, Qi Liu, Ming State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200438 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9798350365429

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000× and 4× improvements than GPU in power consumption and memory overhead. © 2024 IEEE.

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An Efficient Spiking Neural Network Accelerator with Sparse Weight

An Efficient Spiking Neural Network Accelerator with Sparse ...

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IEEE Biomedical circuits and Systems (BIOCAS)

作者： Zilin Wang Yi Zhong Youming Yang Xiaoxin Cui Yuan Wang Key Laboratory of Microelectronics Devices and Circuits (MoE) MPW Center School of Integrated Circuits Peking University Beijing Advanced Innovation Center for Integrated Circuits Beijing China

Spiking neural network (SNN) is a promising generation of neural networks inspired by biology, which has the advantages of high energy efficiency and hardware-friendly. In SNN, the input is not encoded as real-valued activations but as sequences of binary spikes. The weights are usually stored in the form of crossbars. Due to the unstructured pruning and compression in model training, the weights of the SNN model exhibit spatial sparsity. Recently, many matrix compression algorithms have been applied to on-chip weight storage in SNN accelerators. However, when the stored non-zero values exceed a certain proportion, their storage cost is relatively expensive. In this paper, a sparse compressed spiking neural network accelerator based on bit-mask compression algorithm is presented. Implemented on a FPGA platform, the accelerator can achieve the peak performance of 2.56GSOP/s and the energy efficiency of 1.53GSOP/W.

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A centripetal collection image sensor(CCIS) based on back gate modulation achieving 1T submicron pixel

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Science China(Information Sciences) 2022年第4期65卷 282-284页

作者： Liqiao LIU Guihai YU Gang DU Xiaoyan LIU Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Image sensors have been rapidly developed for decades and widely used in many different fields [1, 2]. To achieve high resolution, the pixel size has been scaled down to 1 μm for mass production [3]. Nevertheless, the pixel size has to be further reduced to meet the growing demand for higher resolution. In CMOS image sensor(CIS), the pixel is composed of a photodiode, reset transistor,

关键词： Image sensor submicron pixel back gate modulation pixel crosstalk Silicon on insulator

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Demonstration of vertical Ga2O3 Schottky barrier diodes directly on heavily doped single-crystal substrate using thermal oxidation technology

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The European Physical Journal Special Topics 2025年第2期234卷 283-290页

作者： Liu, Hongyu Han, Shida Lu, Xiaoli Wang, Yuangang Dun, Shaobo Han, Tingting Lv, Yuanjie Feng, Zhihong State Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology School of Microelectronics Xidian University Xi’an China National Key Laboratory of Solid-State Microwave Devices and Circuits Hebei Semiconductor Research Institute Shijiazhuang China

In this letter, by implementing thermal oxidation (TO) technology, vertical Ga2O3 Schottky barrier diodes were directly fabricated on a heavily doped single-crystal (001) β-Ga2O3 substrate without epitaxial growth. The electron concentration in near-surface region of the Ga2O3 substrate was greatly reduced by introducing high-temperature TO processing. X-ray photoelectron spectroscopy (XPS) and photoluminescence (PL) results indicated that the oxygen vacancy (VO) content in the near-surface region was significantly decreased, while a 500–700 nm acceptor-like defect energy level combining multiple gallium vacancy (VGa) generated, and compensated for, the free carriers after annealing in an oxygen-rich atmosphere at high temperature. The annealing temperature and time were analyzed and optimized. Finally, vertical β-Ga2O3 SBDs with a breakdown voltage (Vbr) of 460 V, specific on-resistance (Ron,sp) of 10.5 mΩ·cm2 and a power figure-of-merit (PFOM) of 20.2 MW/cm2, were demonstrated when the annealing temperature and time were 900 °C and 2 h. These results indicate that vertical β-Ga2O3 SBDs can be directly fabricated on a single-crystal substrate without epitaxial growth, providing a new method of reducing the cost of such devices.

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An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applications

An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applicat...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Zhaotong Zhang Yi Zhong Yingying Cui Yawei Ding Yukun Xue Qibin Li Ruining Yang Jian Cao Yuan Wang Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center School of Integrated Circuits Peking University School of Software and Microelectronics Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Inspired by the brain, Spiking Neural Network (SNN) applies temporally sparse spiking communication to gain more bio-mimetic and highly energy efficient computing. The current mainstream platforms for SNN applications are typically the combination of Host+FPGA+Chip Array, which requires an efficient host to preprocess and encode data. It’s not suitable for end-to-end tasks in edge due to its high system power consumption of host and non-negligible high latency of protocol conversion on FPGA. In addition, Convolutional Neural Network (CNN), exhibits strong feature extraction capabilities. Like the brain's visual system, a hierarchical CNN-SNN hybrid network, in which SNN can make use of CNN’s feature extraction capabilities during encoding, can achieve better performance. In this study, we design a 64Neural-Core Array and integrate it with a CNN encoder and a low-power RISC-V CPU within a System-on-Chip (SoC) to enable comprehensive end-to-end hybrid network application support. The proposed heterogeneous SoC is implemented on a Virtex UltraScale+ XCVU9P FPGA, featuring 32.8K neurons, 37.7M synapses and 578GOPS/s peak performance. It processes MNIST classification with a peak throughput of 2022 images per second at frequency of 250MHz. This design gains a balance between high throughput and recognition accuracy simultaneously.

关键词： Accuracy Visual systems Feature extraction Throughput Encoding System-on-chip Convolutional neural networks

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Step-edge controlled fast growth of wafer-scale MoSe_(2)films by MOCVD

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Nano Research 2023年第7期16卷 9577-9583页

作者： Rui Ji Jing Liao Lintao Li Rongji Wen Mengjie Liu Yifeng Ren Jianghua Wu Yunrui Song Minru Qi Zhixing Qiao Liwei Liu Chengbing Qin Yu Deng Yongtao Tian Suotang Jia Yufeng Hao Key Laboratory of Material Physics of Ministry of Education School of Physics and MicroelectronicsZhengzhou UniversityZhengzhou 450052China National Laboratory of Solid State Microstructures College of Engineering and Applied SciencesJiangsu Key Laboratory of Artificial Functional Materialsand Collaborative Innovation Center of Advanced MicrostructuresNanjing UniversityNanjing 210023China State Key Laboratory of Quantum Optics and Quantum Optics Devices Institute of Laser SpectroscopyShanxi UniversityTaiyuan 030006China Collaborative Innovation Center of Extreme Optics Shanxi UniversityTaiyuan 030006China College of Medical Imaging Shanxi Medical UniversityTaiyuan 030001China MIIT Key Laboratory for Low-Dimensional Quantum Structure and Devices School of Integrated Circuits and ElectronicsBeijing Institute of TechnologyBeijing 100081China

Two-dimensional(2D)transition metal dichalcogenides(TMDCs),due to their unique physical properties,have a wide range of applications in the next generation of electronics,optoelectronics,and ***-scale preparation of high-quality TMDCs films is critical to realize these potential *** we report a study on metal-organic chemical vapor deposition(MOCVD)growth of wafer-scale MoSe_(2)films guided by the crystalline step edges of miscut sapphire *** established that the nucleation density and growth rate of MoSe_(2)films were positively correlated with the step-edge density and negatively with the growth *** a certain temperature,the MoSe_(2)domains on the substrate with high step-edge density grow faster than that with low *** a result,wafer-scale and continuous MoSe_(2)films can be formed in a short duration(30 min).The MoSe_(2)films are of high crystalline quality,as confirmed by systematic Raman and photoluminescence(PL)*** results provide an important methodology for the rapid growth of wafer-scale TMDCs,which may promote the application of 2D semiconductors.

关键词： MoSe_(2) nucleation density transition metal dichalcogenides metal-organic chemical vapor deposition(MOCVD) waferscale two-dimensional(2D)semiconductor

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Origin of the unidentified color centers in 4H-SiC from first principles

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Physical Review B 2025年第1期111卷 014106-014106页

作者： Ruirong Bai Dingrong Liu Shiyou Chen Yu-Ning Wu Key Lab of Polar Materials and Devices (MOE) and Department of Electronics East China Normal University Shanghai 200062 China School of Microelectronics and Key Laboratory of Computational Physical Sciences (MOE) Fudan University Shanghai 200433 China

As divacancy (VV) and nitrogen-vacancy (NV) color centers in 4H-SiC have attracted significant interest for their potential in quantum technologies, the origins of the photoluminescence (PL) signals (such as PL5–PL8) observed near the VVs signals (PL1–PL4) remain a mystery. In this paper, multiple defect clusters are designed by combining VVs with intrinsic defects and the common extrinsic elements including oxygen, nitrogen, and hydrogen. Based on the first-principles calculations of the spin configuration, formation energy, zero-phonon line, and zero-field splitting, two configurations of OV0 (one oxygen atom filling the carbon vacancy in VV0) are attributed for PL5 and PL6, and one configuration of NHV0 (one hydrogen atom attached to the nitrogen atom in NV0) is the source of PL8. Further radiative lifetime calculations confirm that these defect clusters are good single-photon sources. Additionally, we found that the OHV+ (OV with one hydrogen atom bonded with the oxygen atom at +1 charge state) are potential color centers with S = 1. In this paper, we provide theoretical insights not only into the preparation of color centers such as PL5, PL6, and PL8 but also into developing color centers that are related to VVs.

关键词： Color centers

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Residual Spiking Neural Network on a Programmable Neuromorphic Hardware for Speech keyword Spotting 16

Residual Spiking Neural Network on a Programmable Neuromorph...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Zou, Chenglong Cui, Xiaoxin Feng, Shuo Chen, Guang Wang, Xinan Wang, Yuan Peking University Key Laboratory of Microelectronics Devices and Circuits School of Integrated Circuits Beijing100871 China Peking University Shenzhen Graduate School Key Laboratory of Integrated Microsystem School of Ece Shenzhen518055 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In recent years, spiking neural networks (SNNs) based on neuromorphic system have shown impressive scalability and energy superiority on lots of intelligent tasks, such as image classification, language understanding and human-computer interaction. In this paper, we propose a novel residual SNN (R-SNN) architecture for speech keyword spotting, which can be easily deployed on a programmable neuromorphic chip. Our experimental results show the proposed R-SNN can achieve 92.08% classification accuracy with about 183 words/second run-time speed and 0.156 mJ/word power performance. © 2022 IEEE.

关键词： Neural networks

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A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Thickness (sub-8nm), Low Thermal Budget (350oC), 100% Initial Chip Yield, Low Power Consumption (0.7 pJ/bit at 2V write voltage), and Prominent Endurance (>1012)

A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Th...

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2023 International Electron devices Meeting, IEDM 2023

作者： Jiang, Pengfei Jiang, Haijun Yang, Yang Tai, Lu Wei, Wei Gong, Tiancheng Wang, Yuan Xu, Pan Lv, Shuxian Wang, Boping Gao, Jianfeng Li, Junfeng Luo, Jun Yang, Jianguo Luo, Qing Liu, Ming Shandong University School of Information Science and Engineering Qingdao China Institute of Microelectronics Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing China Institute of Microelectronics Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Beijing China Zhangjiang Lab Shanghai China

ISBN: (纸本)9798350327670

In this work, we successfully resolve the remanent polarization (Pr) degradation issue, which is caused by the thermal budget decreasing and the film thickness scaling of Hf0.5Zr0.5O2 (HZO), and co-integrate the TiN/HZO/TiN capacitors with large initial Pr and low operating voltage in the Back-End-of -Line (BEOL) of 130nm CMOS technology to provide a 256 Kbit 1T1C FeRAM chip. Firstly, we prove that the Pr degradation is caused by the increasing component of anti-ferroelectric (AFE) phase. Then, utilizing the pre-crystallization engineering and O3 treatment to the TiN bottom electrode (BE), not only the formation of t-phase is effectively suppressed, but also the required annealing temperature is reduced. The enhancement of ferroelectricity is related to the small thermal expansion of TiO2 interface layer, which can induce large tensile stress to HZO during the annealing process. Moreover, the oxidization of TiN BE can prevent it absorbing oxygen from HZO, and the reduced oxygen vacancy (Vo) defects can improve both the retention and TDDB characteristics. Based on the above optimizations, the chip demonstrates 100% initial chip yield, >150mV sense margin after 1012 write cycles, power consumption of 0.7 pJ/bit at 2V write voltage, over 1012 endurance and 10 years retention. © 2023 IEEE.

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A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array

A Hybrid Heterogeneous Neural Network Accelerator based on S...

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IEEE International Conference on Artificial Intelligence circuits and Systems (AICAS)

作者： Zilin Wang Yi Zhong Guang Chen Shuo Feng Youming Yang Xiaoxin Cui Yuan Wang School of Integrated Circuits Peking University Beijing China School of Software and Microelectronics Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China Key Laboratory of Microelectronics Devices and Circuits (MoE) MPW Center Peking University Beijing China

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Spiking neural networks (SNNs) and artificial neural networks (ANNs) are two methods to achieve artificial intelligence. Realizing the long-term and ambitious ideal of a universal artificial intelligence platform requires hardware that supports both SNN and ANN models. ANNs, such as convolutional neural networks (CNNs), are adept at extracting features and have achieved outstanding achievements in many fields. Due to the event-driven processing paradigm, SNNs can achieve competitive accuracy with minimal power usage. The weight accumulation of SNN and ANN is similar, but the activation function is significantly different. How to integrate SNN and ANN on one hardware platform is a challenge. In this paper, we propose a hybrid heterogeneous neural network accelerator that can support both SNN and ANN models. It also has good compatibility with the binary neural network (BNN) models. Our design is implemented on Xilinx XCKU115 FPGA, which can achieve the peak performance of 48.51GSOP/s (SNN) and 26.38GOP/s (ANN). The energy efficiency is 25.8GSOP/W (SNN) and 12.05GOP/W (ANN). Moreover, it supports the SNN-ANN fusion mode, where each row of processing elements (PEs) can independently perform SNN or ANN computation, allowing the design to fully leverage the respective strengths of SNN and ANN.

关键词： Computational modeling Artificial neural networks Spiking neural networks Feature extraction Systolic arrays Hardware Energy efficiency

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