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Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies

Journal of Semiconductors 2025年第6期46卷 66-78页

作者： Yu Song Pengfei Jiang Pan Xu Xueyang Peng Qianqian Wei Qingyi Yan Wei Wei Yuan Wang Xiao Long Tiancheng Gong Yang Yang Eskilla Venkata Ramana Qing Luo Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of SciencesBeijing 100029China Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 101408China I3N-Aveiro Department of PhysicsUniversity of AveiroAveiro3810193Portugal

The novel HfO2-based ferroelectric field effect transistor(FeFET)is considered a promising candidate for next-genera-tion nonvolatile memory(NVM).However,a series of reliability issues caused by the fatigue effect hinder its further ***,a comprehensive understanding of the fatigue mechanisms of the device and optimization strategies is essen-tial for its *** fundamental mechanism of the fatigue effect is attributed to charge trapping and trap generation based on the current studies,and the underlying causes,occurrence locations and specific impacts are analyzed in this *** particular,the asymmetric trapping/detrapping of electrons and holes,as well as the relationship between the ferroelectric(FE)polarization and charge trapping,are given particular *** categorizing and summarizing the current progress,we propose a series of optimization strategies derived based on the fatigue mechanisms.

关键词： FeFET fatigue charge trapping trap generation

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Layer-Valley Hall Effect under Inversion and Time-Reversal Symmetries

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Chinese Physics Letters 2024年第6期41卷 88-97页

作者：赵交交刘贵斌陈鹏姚裕贵张广宇杜罗军 Beijing National Laboratory for Condensed Matter Physics and Key Laboratory for Nanoscale Physics and DevicesInstitute of PhysicsChinese Academy of SciencesBeijing 100190China School of Physical Sciences University of Chinese Academy of SciencesBeijing 100190China Centre for Quantum Physics Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement(MOE)School of PhysicsBeijing Institute of TechnologyBeijing 100081China Beijing Key Lab of Nanophotonics&Ultrafine Optoelectronic Systems School of PhysicsBeijing Institute of TechnologyBeijing 100081China Schoolof Microelectronics Southern University of Science and TechnologyShenzhen 518055China Songshan Lake Materials Laboratory Dongguan 523808China

Hall effects have been the central paradigms in modern physics,materials science and practical applications,and have led to many exciting breakthroughs,including the discovery of topological Chern invariants and the revolution of metrological resistance *** date,the Hall effects have mainly focused on a single degree of freedom(Do F),and most of them require the breaking of spatial-inversion and/or time-reversal *** we demonstrate a new type of Hall effect,i.e.,layer-valley Hall effect,based on a combined layer-valley Do F characterized by the product of layer and valley *** layer-valley Hall effect has a quantum origin arising from the layer-valley contrasting Berry curvature,and can occur in nonmagnetic centrosymmetric crystals with both spatial-inversion and time-reversal symmetries,transcending the symmetry constraints of single Do F Hall effect based on the constituent layer or valley ***,the layer-valley Hall effect is highly tunable and shows a W-shaped pattern in response to the out-of-plane electric ***,we discuss the potential detection approaches and material-specific design principles of layer-valley Hall *** results demonstrate novel Hall physics and open up exotic paradigms for new research direction of layer-valleytronics that exploits the quantum nature of the coupled layer-valley DoF.

关键词： quantum Inversion curvature

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An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow

An Energy-Efficient Differential Frame Convolutional Acceler...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Zhenhui Dai Jiawei Wang Yi Zhong Kunyu Feng Cheng Zhao Yuanyuan Jiang Peiyu Chen Yuan Wang Dunshan Yu Xiaoxin Cui School of Integrated Circuits Peking University Beijing Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center Peking University Beijing School of Software and Microelectronics Peking University Beijing Beijing Advanced Innovation Center for Integrated Circuits Beijing

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Convolutional neural networks require a huge amount of computation in video applications. For some specific tasks, such as surveillance, differential frame convolution reuses inter-frame data and significantly reduces multiplication and accumulation. However, there are still some challenges in improving energy efficiency of differential frame convolution on chips. Firstly, differential frame convolution brings additional on-chip storage for reusing inter-frame data. Secondly, in post-processing of differential frame convolution, there are more memory accessing and arithmetic logic operations. Therefore, sparse working mode is of vital importance for the post-processing. In response to these challenges, this work proposes an on-chip fusion storage architecture for energy-efficient differential frame convolution and a pixel-level pipeline data flow that supports the sparsity of features. The simulation of our accelerator implemented in 28nm CMOS can achieve energy efficiency by 3.09× compared with other state-of-the-art works

关键词： Convolution Surveillance Pipelines Computer architecture Energy efficiency System-on-chip Convolutional neural networks

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A 9.1μW Capacitance-to-Digital Converter for Pressure Sensor Systems 16

A 9.1μW Capacitance-to-Digital Converter for Pressure Senso...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Xia, Qing-Jiang Zhang, Ya-Cong You, You Zhou, Fei Lu, Wen-Gao Peking University School of Software and Microelectronics Beijing100091 China Peking University Key Laboratory of Microelectronic Devices and Circuits Ministry of Education School of Integrated Circuits Beijing100871 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper presents a capacitance-to-digital converter (CDC) for pressure sensor systems, which consists of a front-end circuit and a successive approximation register (SAR) ADC. The front-end circuit uses correlated double sampling technology to eliminate the impact of the low-frequency noise and offset voltage of the operational amplifier. The CDACP and CDACN in the SAR ADC can save power and area as the sampling capacitance of the front-end circuit. The SAR ADC uses bottom plate sampling to avoid various nonlinearities caused by top plate sampling, and a comparator with pre-amplification to reduce the impact of kickback noise. Adjustable reference capacitance (CREF) is designed to expand the detection range of sensor capacitance. The circuit is designed and fabricated in 0.18μm standard CMOS process. While the power supply is 1.8V and the conversion time is 224μs, the power consumption is only 9.1μW. Capacitance resolution of 7.8fF is achieved with sensor capacitance (CSENS) detectable in the range of 10.1pF-21.5pF. © 2022 IEEE.

关键词： Pressure sensors

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A Novel Multiple Modes Resonant Sensor Featuring Blue Sideband Excitation 38

A Novel Multiple Modes Resonant Sensor Featuring Blue Sideba...

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38th IEEE International Conference on Micro Electro Mechanical Systems, MEMS 2025

作者： Xu, Jiao Zheng, Zhuoyue Xi, Jingqian Zhang, Ziqian Liu, Huafeng Zhang, Pan Chen, Jianlin Wang, Chen Kraft, Michael Wang, Yuan Martins, R.P. Mak, Pui-In Huazhong University of Science and Technology Moe Key Laboratory of Fundamental Physical Quantities Measurement Pgmf School of Physics Wuhan430074 China University of Macau Institute of Microelectronics State Key Laboratory of Analog and Mixed-Signal Vlsi 999078 China Peking University National Key Laboratory of Advanced Micro and Nano Manufacture Technology School of Integrated Circuits 100871 China Shanghai University School of Microelectronics 200444 China Ku Leuven Department of Electrical Engineering-MNS Leuven3000 Belgium

ISBN: (纸本)9798331508890

This paper reports a novel MEMS resonant structure functioning as a baseline resonant electrostatic force/temperature sensor, highlighting its substantial potential in sensing applications. The resonator, characterized by a dual-cosine structure, is capable of simultaneous multiple resonant modes actuation within the 300 kHz range, through a sole-source drive approach using the recent emerging Blue Sideband Excitation (BSE) technique. This method enables a distinctive multi-modal response, essential for multi-parameter measurements. The research focuses on the sensor's temperature characteristics, electrostatic perturbation sensitivity, and noise floor. Notably, the study reveals intriguing temperature responses across different modes, where certain modes exhibit a significant frequency rise with increasing temperature, this is counter-intuitive with common MEMS resonator devices, prompting further investigation into the underlying mechanisms. The analysis of electrostatic perturbation sensitivity and noise background further unfolds the resonator's performance under various excitation conditions, laying a foundation for advancing sensor functionality, and providing solid evidence on the viability of the subject. To sum up, this study highlights the resonator's potential as a high-precision sensor, opening new opportunities for MEMS sensor design and multi-parameter measurement applications. © 2025 IEEE.

关键词： Microchannels

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Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers 14

Low Power Readout Integrated Circuit with PFM-based ADCs Emp...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Zhou, Ye Yu, Shanzhe Lu, Wengao Yu, Dunshan Zhang, Yacong Chen, Zhongjian Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

This paper presents a low power readout integrated circuit (ROIC) with 12-bit two-stage column-wise ADCs for 25μm-pitch 640×480 silicon diode uncooled infrared imagers. A novel two-stage column-wise ADC composed of a pulse frequency modulation (PFM)-based ADC for coarse conversion and a single-slope ADC for fine conversion is proposed. The proposed ADC meets the requirements for power budget, conversion rate, and linearity performance in column-wise ADC application for uncooled infrared imagers. The PFM-based ADC adopts a passive integrator and an optimized comparator structure to reduce static power consumption. The ROIC is designed in standard 0.18μm 1P5M CMOS process. Simulation shows that the SNR and nonlinearity is 74dB and 0.12%, respectively. Power consumption of the ROIC is 54mW and each column ADC consumes only 10μW. © 2021 IEEE.

关键词： Budget control

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High Frame Rate High Linearity Low Power DROIC for 30μm-Pitch Cryogenic Infrared FPAs 14

High Frame Rate High Linearity Low Power DROIC for 30μm-Pit...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Niu, Yuze Gu, Yuting Liu, Fengqing Zhou, Fei Yu, Shanzhe Lu, Wengao Zhang, Yacong Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

This paper presents a pixel circuit with high frame rate, high linearity, and low power consumption. This pixel circuit is applied in a digital readout integrated circuit (DROIC) of 320×256 infrared focal plane array(IRFPA). The proposed single slope ADC is deployed in the proposed pixel circuit, which improves linearity and power consumption of the DROIC. The proposed pixel circuit is fabricated using 180nm 1P5M CMOS process with 30μm pixel pitch. Pixel power consumption is 406nW. Frame rate of the proposed DROIC is 1KHz. Nonlinearity of the quantization is lower than 0.8%. © 2021 IEEE.

关键词： Electric power utilization

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Ferroelectric-controlled graphene plasmonic surfaces for all-optical neuromorphic vision

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Science China(Technological Sciences) 2024年第3期67卷 765-773页

作者： CHEN JianBo LIU Yu LI ShangDong LIN Lin LI YaDong HUANG Wen GUO JunXiong School of Electronic Information and Electrical Engineering Institute for Advanced StudyChengdu UniversityChengdu 610106China School of Integrated Circuits Tsinghua UniversityBeijing 100084China School of Integrated Circuits(National Exemplary Schoolof Microelectronics) Universityof Electronic Science and Technologyof China Chengdu 610054China Jincheng Research Institute of Opto-mechatronics Industry Jincheng 048000China Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems Jincheng 048000China Engineering Research Center of Digital Imaging and Display Ministry of EducationSoochow UniversitySuzhou 215006China

Artificial visual systems can recognize desired objects and information from complex environments, and are therefore highly desired for pattern recognition, object detection, and imaging applications. However, state-of-the-art artificial visual systems with high recognition performances that typically consist of electronic devices face the challenges of requiring huge storage space and high power consumption owing to redundant data. Here, we report a terahertz(THz) frequency-selective surface using a graphene split-ring resonator driven by ferroelectric polarization for efficient visual system applications. The downward polarization of the ferroelectric material offers an ultrahigh electrostatic field for doping p-type graphene with an anticipated Fermi level. By optimizing the geometric parameters of the devices and modulating the carrier behaviors of graphene, our plasmonic devices exhibit a tunable spectral response in a range of 1.7–6.0 THz with continuous transmission values. The alloptical neural network using graphene plasmonic surfaces designed in this study exhibited excellent performance in visual preprocessing and convolutional filtering and achieved an ultrahigh recognition accuracy of up to 99.3% in training the Modified National Institute of Standards and Technology(MNIST) handwritten digit dataset. These features demonstrate the great potential of graphene plasmonic devices for future smart artificial vision systems.

关键词： graphene plasmon ferroelectric frequency selective surface artificial vision system

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First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip

First Demonstration of a Design Methodology for Highly Relia...

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2023 IEEE Symposium on VLSI Technology and circuits, VLSI Technology and circuits 2023

作者： Gong, Tiancheng Xu, Lihua Wei, Wei Jiang, Pengfei Yuan, Peng Nie, Bowen Huang, Yuanquan Wang, Yuan Yang, Yang Gao, Jianfeng Li, Junfeng Luo, Jun Wang, Lingfei Yang, Jianguo Luo, Qing Li, Ling Chung, Steve S. Liu, Ming Institute of Microelectronics Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing China Institute of Microelectronics Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Beijing China Institute of Electronics National Yang Ming Chiao Tung University Taiwan

ISBN: (纸本)9784863488069

In achieving a reliable operation of FRAM arrays at high temperature (300K-400K), we provide an optimized operation design methodology considering the temperature effect on 128kb ITIC FRAM chip for the first time. Firstly, we found that the conventional voltage selection scheme in ITIC FRAM array is not applicable at high temperature since the Pr value read by low voltage decreases at high temperature, leading to a poor yield. Then, the mechanism of Pr degradation under high temperature is systematically investigated through material characterizations and electrical measurements. It was found that the increase of the internal electric field (Ebias) caused by electron de-trapping mainly contributes to the Pr degradation. Moreover, a KMC model considering Ebias is developed, and the optimum voltage, which can mitigate the temperature effect from 300K-400K, is predicted. This predicted voltage is finally validated on 128kb ITIC FeRAM chip, and excellent properties including non-volatile (150°C >106s) and high endurance (>1011) under the predicted voltage are also demonstrated. © 2023 JSAP.

关键词： Temperature

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A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm Pitch 320 ×256 LWIR FPAs 14

A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm ...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Niu, Yuze Liu, Bingxin Kong, Jiaqi Zhou, Fei Yu, Shanzhe Lu, Wengao Zhang, Yacong Chen, Zhongjian Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

A low-power and high-dynamic range ADC-based 320×256 size digital readout integrated circuit for infrared focal plane arrays is proposed in this paper. Compared with the traditional structure, the proposed pixel-level ADC structure based on ring oscillator can achieve higher dynamic range and lower power consumption. The design is based on 0.18μm 1P5M CMOS process, and the pixel circuit pitch is 30μm. The simulation results show that the average power consumption of the proposed single pixel-level ADC is 1.36μW. The charge handling capacity of the pixel is 2.8Ge-;the dynamic range is 96.32dB, and the non-linearity is 0.76%. © 2021 IEEE.

关键词： Pixels

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