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International Electron devices Meeting (IEDM)

作者： Chao Li Jie Yu Xumeng Zhang Zhaohao Zhang Fangduo Zhu Siyuan Ouyang Pei Chen Lingli Cheng Gaobo Xu Qingzhu Zhang Huaxiang Yin Qi Liu Ming Liu State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000x and 4x improvements than GPU in power consumption and memory overhead.

关键词： Performance evaluation Power demand Neuromorphics Memory management Graphics processing units Trajectory Vehicle dynamics Synapses Long short term memory FeFETs

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A Fully BEOL-Compatible (300°C Annealing) IGZO FeFET with Ultra-High Memory Window (10V) and Prominent Endurance (109)

A Fully BEOL-Compatible (300°C Annealing) IGZO FeFET with U...

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International Electron devices Meeting (IEDM)

作者： Pan Xu Pengfei Jiang Yang Yang Xueyang Peng Wei Wei Tiancheng Gong Yuan Wang Xiao Long Jiebin Niu Zhongguang Xu Chenxin Zhu Zhenhua Wu Qing Luo Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China University of Science and Technology of China Hefei Anhui China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

HfO 2 -based FeFET paves the way for the next generation NVM thecnology, however, demands for high memory window (MW) and roubust reliability (especially the endurance) cannot be combined in the current reported devices, and the contradiction of high MW and low thermal budget (aiming for BEOL compatibility) also needs to be solved. In this work, we propose an integrated ferroelectric (FE) Hf 0.5 Zr 0.5 O 2 (HZO) and amorphous In-Ga-Zn-O (a-IGZO) channel FeFET with a maximum 10V MW and prominent endurance up to 10 9 . Workfunction (WF) engineering is utilized to regualte the intrinsic $\mathrm{V}_{\mathrm{t}}$ to improve the PGM/ERS efficiency with full-loop polarization switching, and the adopted Mo gate can effectively reduce the thermal budget to 300°C ensuring a fully BEOL compatibility. Then with O 3 -plasma treatment to the gate electrode, the introduced tunneling layer can futher improve the MW by gate charge injection. The demonstrated FeFET shows great 3-bit/cell storage ability without states overlapping, high $\mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}}$ ratio $(>10^{7})$ , as well as great linearity and high $\mathrm{G}_{\max}/\mathrm{G}_{\min}$ (286) during synaptic weight modulation.

关键词： Performance evaluation Nonvolatile memory Thermal engineering Modulation Switches Logic gates Tunneling Reliability FeFETs Next generation networking

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Associative learning of a three-terminal memristor network for digits recognition

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Science China(Information Sciences) 2023年第2期66卷 209-218页

作者： Yiming REN Bobo TIAN Mengge YAN Guangdi FENG Bin GAO Fangyu YUE Hui PENG Xiaodong TANG Qiuxiang ZHU Junhao CHU Chungang DUAN Key Laboratory of Polar Materials and Devices (MOE) Ministry of Education Department of ElectronicsEast China Normal University Zhejiang Lab Institute of Microelectronics Beijing Innovation Center for Future Chips (ICFC) Tsinghua University Collaborative Innovation Center of Extreme Optics Shanxi University

Imitating the associative intelligence of the biological brain is attractive but is poorly achieved in hardware because the complex tunable connection in neural networks is difficult to reproduce. We develop a circuit composed of a three-terminal memristor network to reproduce the biological conditioning process artificially. The synaptic weight between co-firing neurons is strengthened simultaneously by generating a feedback signal from the integrate-and-fire neuron to the gate of the synaptic memristor. The network allows the multi-associative capacity of recalling more than one digit in one circuit. Both single and multi-associative learning for recalling digital images are achieved. Furthermore, all 10 digital images from “0” to “9” are successfully recalled in an associative network with such paralleling circuits. Assisted by this associative layer, a typical classification network effectively improves the recognition rate for fragmentary digital *** work sheds light on brain-inspired artificial associative memory and provides a strategy for applications,such as object recognition with partial features and similar scenes.

关键词： artificial intelligence associative learning memristor classification network

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High-gain optical parametric amplification with continuous-wave pump using domain-engineered thin film lithium niobate waveguide

arXiv

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arXiv 2024年

作者： Chen, Mengwen Wang, Chenyu Jia, Kunpeng Tian, Xiao-Hui Tang, Jie Zhu, Chunxi Gu, Xiaowen Zhao, Zexing Wang, Zikang Ye, Zhilin Tang, Ji Zhang, Yong Yan, Zhong Qian, Guang Jin, Biaobing Wang, Zhenlin Zhu, Shi-Ning Xie, Zhenda Key Laboratory of Optoelectronic Devices and Systems with Extreme Performances of MOE Collaborative Innovation Center of Advanced Microstructures Nanjing University Nanjing210093 China National Key Laboratory of Solid-State Microwave Devices and Circuits Nanjing Electronic Devices Institute Nanjing210016 China Nanzhi Institute of Advanced Optoelectronic Integration Nanjing211800 China School of Integrated Circuits Nanjing University of Information Science and Technology Nanjing210044 China Purple Mountain Laboratories Nanjing211111 China

While thin film lithium niobate (TFLN) is known for efficient signal generation, on-chip signal amplification remains challenging from fully integrated optical communication circuits. Here we demonstrate the first continuous-wave-pump optical parametric amplification (OPA) using an x-cut domain-engineered TFLN waveguide, with high gain over the telecom band up to 13.9 dB, and test it for high signal-to-noise ratio signal amplification using a commercial optical communication module pair. Fabricated in wafer scale using common process as devices including modulators, this OPA device marks an important step in TFLN photonic integration. Copyright © 2024, The Authors. All rights reserved.

关键词： Optical parametric amplifiers

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High quality 6-inch single-crystalline AlN template for E-mode HEMT power device

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Journal of Semiconductors 2025年第3期46卷 96-101页

作者： Zhiwen Liang Shangfeng Liu Ye Yuan Tongxin Lu Xiaopeng Li Zirong Wang Neng Zhang Tai Li Xiangdong Li Qi Wang Shengqiang Zhou Kai Kang Jincheng Zhang Yue Hao Xinqiang Wang Songshan Lake Materials Laboratory Dongguan 523808China Guangzhou Wide Bandgap Semiconductor Innovation Center Guangzhou Institute of TechnologyXidian UniversityGuangzhou 510555China School of Physical Sciences Great Bay UniversityDongguan 523808China Helmholtz-Zentrum Dresden-Rossendorf Institute of Ion Beam Physics and Materials ResearchBautzner Landstrasse 40001328DresdenGermany Dongguan Institute of Opto-Electronics Peking University Dongguan 523808China Sinopatt.Technology Co. LtdSongshan LakeDongguan 523808China State Key Laboratory of Artificial Microstructure and Mesoscopic Physics School of PhysicsNan-oOptoelectronics Frontier Center of Ministry of Education(NFC-MOE)Peking UniversityBeijing 100871China State Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology School of MicroelectronicsXidian UniversityXi’an 710071China

In the present work,the high uniform 6-inch single-crystalline AlN template is successfully achieved by high temperature annealing technique,which opens up the path towards industrial application in power ***,the outstanding crystalline-quality is confirmed by Rutherford backscattering spectrometry(RBS).In accompanied with the results from X-ray diffraction,the RBS results along both[0001]and[1213]reveal that the in-plane lattice is effectively reordered by high temperature *** addition,the constantΦ_(epi)angle between[0001]and[1213]at different depths of 31.54°confirms the uniform compressive strain inside the AlN *** from the excellent crystalline quality of AlN template,we can epitaxially grow the enhanced-mode high electron mobility transistor(HEMT)with a graded AlGaN buffer as thin as only~300 *** an ultra-thin AlGaN buffer layer results in the wafer-bow as low as 18.1μm in 6-inch wafer *** fabricated HEMT devices with 16μm-L_(GD)exhibits a threshold voltage(V_(TH))of 1.1 V and a high OFF-state breakdown voltage(V_(BD))over 1400 ***,after 200 V high-voltage OFF-state stress,the current collapse is only 13.6%.Therefore,the advantages of both 6-inch size and excellent crystallinity announces the superiority of single-crystalline AlN template in low-cost electrical power applications.

关键词： single-crystalline allium nitride template E-mode HEMT

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First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip

First Demonstration of a Design Methodology for Highly Relia...

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Symposium on VLSI Technology

作者： Tiancheng Gong Lihua Xu Wei Wei Pengfei Jiang Peng Yuan Bowen Nie Yuanquan Huang Yuan Wang Yang Yang Jianfeng Gao Junfeng Li Jun Luo Lingfei Wang Jianguo Yang Qing Luo Ling Li Steve S. Chung Ming Liu State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Institute of Electronics National Yang Ming Chiao Tung University Taiwan

In achieving a reliable operation of FRAM arrays at high temperature (300K-400K), we provide an optimized operation design methodology considering the temperature effect on 128kb ITIC FRAM chip for the first time. Firstly, we found that the conventional voltage selection scheme in ITIC FRAM array is not applicable at high temperature since the P r value read by low voltage decreases at high temperature, leading to a poor yield. Then, the mechanism of P r degradation under high temperature is systematically investigated through material characterizations and electrical measurements. It was found that the increase of the internal electric field $(\mathrm{E}_{\mathrm{b}\mathrm{i}\mathrm{a}\mathrm{s}})$ caused by electron de-trapping mainly contributes to the P r degradation. Moreover, a KMC model considering $\mathrm{E}_{\mathrm{b}\mathrm{i}\mathrm{a}\mathrm{s}}$ is developed, and the optimum voltage, which can mitigate the temperature effect from 300K-400K, is predicted. This predicted voltage is finally validated on 128kb ITIC FeRAM chip, and excellent properties including non-volatile $(150^{\circ}\mathrm{C}\gt10^{6}\mathrm{s})$ and high endurance $(\gt10^{11})$ under the predicted voltage are also demonstrated.

关键词：

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Influence of Back Gate Bias on the Hot Carrier Reliability of DSOI nMOSFET

Influence of Back Gate Bias on the Hot Carrier Reliability o...

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Annual International Symposium on Reliability Physics

作者： Xinyi Zhang Kewei Wang Fang Wang Jiangjiang Li Zhicheng Wu Duoli Li Bo Li Jianhui Bu Zhengsheng Han Institute of Microelectronics of Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of Sciences Beijing China State key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

The hot carrier reliability under different back-gate bias in DSOI nMOSFET is studied. Reverse back-gate bias results in an over-all larger time exponents than the forward back-gate bias, which is attributed to the increased lateral electric field (as supported by TCAD simulation) and consequently a stronger interface state generation (related to SVE mechanisms). Such strong time acceleration is crucial for long term reliability prediction under circuit operation. The abnormal deviation among threshold voltage shift, linear/saturation drain current degradation is observed: through careful inspection of the degradation of the I- V characteristics, the competing role of the interface state generation and hot hole trapping is revealed, with a virtual channel shortening effect as supported by the increased DIBL values.

关键词： Degradation Simulation Hot carriers MOSFET circuits Logic gates Threshold voltage Interface states

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Silicon Vapor Chamber with Hierarchical Micro-/Nano Wicks

Silicon Vapor Chamber with Hierarchical Micro-/Nano Wicks

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International Conference on (ICEPT) Electronic Packaging Technology

作者： Deyin Zheng Xin Yu Lin Chen Wei Wang School of Microelectronics Tianjin University Tianjin China School of Integrated Circuits Peking University Beijing China MOE Key Laboratory of Power Station Energy Transfer Conversion and System North China Electric Power University Beijing China

ISBN: (数字)9798350353808

ISBN: (纸本)9798350353815

A two-step processing method is developed for the fabrication of micro- and nano hierarchical wick structures on silicon substrate. Deep reaction ion etching (DRIE) was used to fabricate the primary wick, while the secondary wick structure was formed by electrochemical (EC) etching on the surface of the primary wick. The processing results show that the fabricated hierarchical wick structures consist of dense arrays of microscale trench and a uniformly distributed nanoporous layer with pore diameters less than 50nm. The merit of these hierarchical structures was demonstrated by thermal tests on the silicon vapor chamber integrated with such wicks. A prototype of the vapor chamber with 30 mm × 25 mm × 1.5 mm in dimension was developed as a passive heat spreader for thermal management of electronics. Thermal performance results indicate that the integration of hierarchical wick structures can significantly reduce the thermal resistance by ~50% compared with samples integrated with only microwick structures. Such an optimization on the thermal resistance indicates that integration of such hierarchical wick could be a promising method for the optimization of silicon-based thermal management devices.

关键词： Thermal management of electronics Heating systems Temperature distribution Thermal resistance Thermal management Silicon Etching

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Fabrication and Performance Assessment of High-Mobility Sige Channel P-Type SOI FinFET Transistor

Fabrication and Performance Assessment of High-Mobility Sige...

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IEEE Electron devices Technology and Manufacturing Conference (EDTM)

作者： Zijing Zhang Yuchen Wu Yan Li Huaizhi Luo FanYu Liu Yongliang Li Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing Chinese Academy of Sciences Institute of Microelectronics Beijing China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of Sciences Beijing China School of Applied Science Beijing Information Science and Technology University China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

In this work, we successfully fabricated P-type FinFET transistor featuring SiGe channel on a silicon-on-insulator (SOI) substrate by adopting the SiGe epitaxy and etching processes. Under the gate length of 40 nm, its subthreshold swing (SS) is $82 \text{mV} /$ dec and $\mathrm{I}_{\text{on}} / \mathrm{I}_{\text{off}}$ ratio is $\sim 10^{6}$ . Its excellent electrical and reliability characteristics reveal that this SiGe SOI FinFET is a potential candidate for the future advanced nodes.

关键词： Scanning electron microscopy Semiconductor device reliability Logic gates FinFETs Silicon Epitaxial growth Plasmas Transistors Substrates Silicon germanium

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A High Dynamic Range Pixel Circuit with High-voltage Protection for 128×128 Linear-mode APD Array 15

A High Dynamic Range Pixel Circuit with High-voltage Protect...

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15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

作者： Gu, Yuting Lu, Wengao Niu, Yuze Zhang, Yacong Chen, Zhongjian Key Laboratory of Microelectronic Devices and Circuits Peking University Department of Microelectronics China

ISBN: (纸本)9781728162355

This paper presents a high dynamic range pixel circuit with high-voltage protection for 128×128 Linear-mode avalanche photodiode (LM-APD) array. The pixel circuit includes a high-voltage transistor, a pixel-level analog-to-digital converter (ADC), and a high-voltage protection circuit based on circuit-shared. Through circuit-shared, the pixel-level A/D conversion and high-voltage protection are completed efficiently. Meanwhile, the dynamic range of the entire circuit is greatly improved. The chip is designed in 0.18µm CMOS process. The frame rate is 100Hz and the resolution is 16bit. The simulation results indicate that the dynamic range is 94dB and the power consumption is 5µW per pixel. The pixel pitch is 100µm, which can be reduced further with smaller APD detector. © 2020 IEEE.

关键词： Surge protection

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