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ECS Meeting Abstracts 2014年第38期MA2014-01卷

作者： Tao Yang Qiang Xu Yihong Lu Zhang Yue Jing Xu Guilei Wang Hushan Cui Junfeng Li Jiang Yan Chao Zhao Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Institute of Microelectronics of Chinese Academy of Sciences

Beyond 32nm node, gate last integration scheme had become a mainstream because it ensures the thermal stability of high-kand metal gate stack by applying the metal gate after the high temperature source/drain activation anneal. During HKMG gate last CMOS integration, metal gate chemical and mechanical planarization (CMP) is an indispensable and key process step. Al metal gate is firstly introduced from 32nm node by Intel, which brought new process challenges for Al filling and correspondent CMP. We adopted W as metal gate using atomic layer deposition (ALD) method, besides of ALD W ideal fill capability, compatibility with traditional W CMP is also taken into account. Different ALD W layers were prepared using B2H6 base and SiH4 base. Removal rate, surface roughness and electrochemical characteristic in W slurry were examined for two types ALD W. The removal rate of B2H6 base ALD W was high than that of SiH4 base. RMS of ALD W with SiH4 and B2H6 base were all less than 1nm after CMP. The adhesion of SiH4 base ALD W between W and barrier layer was stronger than that of B2H6 base ALD W. B2H6 base ALD W has better filling ability than that of SiH4 base ALD W for small size gate trench. Compared with single base ALD W filling metal gate, B2H6 base ALD W filling with SiH4 base ALD W pre-treatment was more benefit to decrease metal gate dishing after CMP process.

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Processing Challenges of CMOS integration of Finfets with All-Last Gate Stacks

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ECS Meeting Abstracts 2014年第36期MA2014-01卷

作者： Chao Zhao Tianchun Ye Huilong Zhu Huaxiang Yin Jun Luo Hong Yang Chunlong Li Tao Yang Hushan Cui Jianfeng Gao Guilei Wang Qiang Xu Jinjuan Xiang Yongkui Zhang Zhiguo Zhao Jinbiao Liu Peizhen Hong Lingkuan Meng Tingting Li Junjie Li Xiaobin He Wenjuan Xiong Dahai Wang Yihong Lu Junfeng Li Huicai Zhong Haizhou Yin Jiang Yan Wenwu Wang Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Institute of Microelectronics of Chinese Academy of Sciences

FinFETs with 20nm BEOL with one generation improvement in performance and power efficiency has announced for mass production by leading IC companies. The processing details, however, have never been reported. In this talk, processing challenges of CMOS integration of FinFETs with all-last gate stacks is presented based on our recent results. Special processing issues in Fin and the replacement gate (RMG) formation, RMG filling with high-k/metal gate and self-aligned contact (SAC) module will be discussed. It is found that the etching of dummy gate of FinFETs behaves differently from that in planar MOSFETs. Thick enough dummy SiO2 is needed for protecting the Fin from plasma damage during dummy gate etch. Wet removal of dummy SiO2 in gate area faces also the risk of Fin damage, due to galvanic corrosion, and thus prefers to a thin SiO2 for control of the wet processing window. It is shown that TaN coverage of the channel area is important in single dielectric dual metal gate stack, where a p-FET stack is first deposited in both n- and p-area, and then the top work function metals in n-area will be removed before n-FET metal deposition. ALD TaN is studied systematically for the the etch stopper application. It is found that the largest issue in the CMOS integration of the FinFETS is n-work function metal deposition. Poor TiAl coverage induces large Vt variation. ALD TiAl could be a good solution for n-work function metal deposition. Filling of the RMG, which has extremely large AR in FinFETs, and SAC is a big challenge. A systematic study of ALD W shows that its advantage in properties such as adhesion, conformality and good constraint by TiN barrier enables good fill of the gaps. Electrical characterizations of the FinFETs are presented in order to show the impact of the above issues to device behavior variation.

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Sige Selective Epitaxial Growth Process for 22 Nm Node CMOS and Beyond

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ECS Meeting Abstracts 2014年第44期MA2014-01卷

作者： Guilei Wang Ye Tianchun Jun Luo Changliang Qin Yefeng Xu Tao Chen Qiang Xu Peizhen Hong Tao Yang Chunlong Li Gaobo Xu Jiahan Yu Haizhou Yin Junfeng Li Jiang Yan Huilong Zhu Chao Zhao Henry H Radamson Institute of Microelectronics of Chinese Academy of Sciences Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences KTH Royal Institute of Technology

As CMOS technology downscales into 22nm and beyond nodes, strain engineering technologies are widely used to improve the short channel effect and enhance MOS mobility to make high performance devices. During these technology developments, SiGe selective epitaxial growth has been used as stressor material in source and drain (S/D) region to induce uniaxial strain in channel region [1]. In order to further enhance the MOS channel mobility, the recess shape has to be designed to create maximum strain from the grown SiGe layers. To achieve this goal the etch step has been modified to elaborate a sigma (∑) shape recess and a high Ge content film is deposited in S/D regions [2]. Then SiGe epitaxy process becomes sensitive to surface quality of the recess where a careful etching and in- and ex-situ cleaning are demanded. In this study, selective Si1-xGex growth (0.25≤x≤0.35) with boron concentration of 1-3×1020 cm-3for 22nm node CMOS process has been investigated (see Fig.1). The selectivity issue has examined/tuned around the gate region where both nitride and oxide layers were presented and the thermal budget was decreased to 800 °C to preserve the sigma shape in the S/D regions (see Fig.2). The structures contained two Si1-xGex layers; where the recess was filled first with Si0.65Ge0.35 and then a cap Si0.75Ge0.25layer to elevate the S/D regions. The purpose for having the elevated SiGe cap layer was to avoid strain relaxation in the SiGe bottom layer during the Ni-silicidation process. The Ge content in epi-layers on the chips was measured directly by rocking curves (RCs) using high-resolution x-ray diffraction (HRXRD). RC were done at (113) reflection where the incident beam is as low as 2.6° and a large area of sample containing an enormous of number of transistors could be covered by x-ray beam. These RCs were simulated by the Takagi-Taupin equations and compared to the experimental curves in order to obtain the high precision data analysis[3]. In these measurements

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Investigations of fermi level pinning and dipole formation in TiN/HfO2/SiO2/Si stacks

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2012 International Conference on Material Sciences and Manufacturing technology, ICMSMT 2012

作者： Zhang, Jing Wang, Xiaolei Han, Kai Wang, Wenwu Zhao, Chao Chen, Dapeng Ye, Tianchun Microelectronics Department North China University of Technology Beijing 100041 China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences Beijing 100029 China

ISBN: (纸本)9783037855768

Fermi level pinning (FLP) and dipole formation in TiN/HfO2/SiO2/Si stacks are investigated. The magnitude of FLP at TiN/HfO2 interface is estimated to be ~0 V based on dipole theory using concepts of interfacial gap states and charge neutrality level (CNL). The dipole amount at HfO2/SiO2 interface is experimentally extracted to be +0.33 V. These results show that dipole formation at HfO2/SiO2 interface is important for tuning flatband voltage of the TiN/HfO2/SiO2/Si stacks. Possible origin of dipole formation is demonstrated and attributed to be lower CNL of HfO2 compared with that of SiO2/Si stacks. © (2013) Trans Tech Publications, Switzerland.

关键词： Silica

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Investigation on optical properties of 3C/4H structure silicon carbide

Investigation on optical properties of 3C/4H structure silic...

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第一届全国椭圆偏振光谱学研讨会

作者： Deng Xie Zhi Ren Qiu Bin Xin Ren-Xu Jia Yu-Ming Zhang Huirong Su Ting Mei Zhe Chuan Feng Laboratory of Nanophotonic Functional Materials and Devices Institute of Optoelectronic Material and TechnologySouth China Normal UniversityGuangzhou 510631China State Key Laboratory of Optoelectronic Materials and TechnologiesSun Yat-Sen UniversityGuangzhou 510275China Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and DevicesSchool of MicroelectronicsXidian UniversityXi''an 710071China Genuine Optronics LimitedShanghai 200235China Key Laboratory of Space Applied Physics and ChemistryMinistry of Education and Shaanxi Key Laboratory of Optical Information TechnologySchool of ScienceNorthwestern Polytechnical UniversityXi''an 710072China Institute of Photonics and Optoelectronics and Department of Electrical EngineeringNational Taiwan UniversityTaipeiTaiwan106-17

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Process Parameters Effect on Deep Silicon Etching for High Density Capacitor Structure

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ECS Meeting Abstracts 2014年第39期MA2014-01卷

作者： Lingkuan Meng Jiang Yan Chunlong Li Junjie Li Peizhen Hong Jun Luo Junfeng Li Chao Zhao Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China Institute of Microelectronics of Chinese Academy of Sciences

In deep silicon etching process, there have been many investigations on etching rate. However, only few published papers mentioned the sidewall roughness, which is a critical issue for NMES/MEMS application. In this work, we encountered a special phenomenon: sidewall damage, which was firstly observed during deep silicon etching. Various process parameters such as chamber pressure, bias power, passivation gas flow and etch time have been investigated using a conventional two steps Bosch process for high density Metal-insulator-metal (MIM) capacitor application. During the etching, obvious sidewall damage can be observed in the etched trench sidewall. It can be noted its starting depth has a close dependence on process parameters such as chamber pressure and bias power, which play a significant role influencing etching profile and trench depth. At a lower pressure, a smooth sidewall without any damage can be achieved. With pressure increasing above a certain value, sidewall damage has almost occurred in the full trench, which will lead a series of severe issues such as poor conformal deposition of high-k insulation film, discontinuity of the electrode layer, and reliability failures in MIM capacitor structure. On the other hand, at a given pressure, bias power has a direct effect on etching profile and sidewall damage. As bias power increases, etching profile becomes more negative from vertical one. In particular, sidewall damage is not located in certain depth range but distributed in almost whole trench sidewall and, multi-bowing profile can be seen with increasing etching depth. According to the experimental results, an etching mechanism has been presented to explain the etching phenomena by the ion angular distribution function (IADF) fundamental. Finally, by optimizing process parameters, a perfectly smooth profile without any sidewall damage can be obtained having an aspect ratio as high as 30 with 5μm width.

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Electronic structures and optical properties of a SiC nanotube with vacancy defects

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Journal of Semiconductors 2013年第2期34卷 1-5页

作者：宋久旭杨银堂王平郭立新张志勇 Key Laboratory of Ministry of Education for Wide Band Gap Semiconductor Materials and Devices School of MicroelectronicsXidian University School of Electronic Engineering Xian Shiyou University School of Science Xidian University Information Science and Technology Institution Northwest University

Based on first-principle calculations, the electronic structures and optical properties of a single-walled （7, 0） SiC nanotube （SiCNT） with a carbon vacancy defect or a silicon vacancy defect are investigated. In the three silicon atoms around the carbon vacancy, two atoms form a stable bond and the other is a dangling bond. A similar structure is found in the nanotube with a silicon vacancy. A carbon vacancy results in a defect level near the top of the valence band, while a silicon vacancy leads to the formation of three defect levels in the band gap of the nanotube. Transitions between defect levels and energy levels near the bottom of the conduction band have a close relationship with the formation of the novel dielectric peaks in the lower energy range of the dielectric function.

关键词： SiC nanotube vacancy defect first-principles study electronic structures optical properties

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The Applications of Plasma Immersion Ion Implantation to Crystalline Silicon Solar Cells

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Energy Procedia 2013年 38卷 289-296页

作者： Bangwu Liu Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China

In the paper, plasma immersion ion implantation (PIII) has been put forward to texture and dope the silicon for solar cells. The influence of PIII parameters on the surface structure has been investigated. The various surface structure of the silicon can be obtained by PIII texturing. Compared with acid texturing solar cells, the average conversion efficiency of PIII texturing solar cells has been improved by 0.7% absolute gain. The characteristics of PN junction formed by PIII doping have been investigated. The conversion efficiency of the solar cell can reach as high as 14.84% using PIII doping.

关键词： plasma immersion ion implantation texturing doping solar cell

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Influence of the texturing structure on the properties of black silicon solar cell

Influence of the texturing structure on the properties of bl...

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作者： Zhong, Sihua Liu, Bangwu Xia, Yang Liu, Jinhu Liu, Jie Shen, Zenan Xu, Zheng Li, Chaobo Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China Institute of Solar Energy in School of Science Beijing Jiaotong University Beijing 100044 China

An optimized textured structure is a key for high efficiency multi-crystalline silicon solar cell. In this work, black silicon wafers with various structures have been successfully produced by plasma immersion ion implantation. The surface morphology, reflectance and internal quantum efficiency have been investigated by atomic force microscope, spectrophotometer and quantum efficiency measurement system, respectively. Results show that nanohillocks with average height of 150-600 nm have been generated on black silicon surfaces by different texturing conditions, and the reflectance over the wavelength from 300 nm to 1100 nm decreases with increasing the height of nanohillocks, whereas the internal quantum efficiency worsens. The solar cell based on the optimized nanohillocks height of 300 nm yeilds efficiency of 15.99% with short circuit current of 34.0 mA/cm2. © 2012 Elsevier B.V.

关键词： Atomic force microscopy

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Channel Hot-Carrier degradation characteristics and trap activities of high-k/metal gate nMOSFETs

Channel Hot-Carrier degradation characteristics and trap act...

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International Symposium on Physical & Failure Analysis of Integrated Circuits

作者： Weichun Luo Hong Yang Wenwu Wang Hao Xu Shangqing Ren Bo Tang Zhaoyun Tang Jing Xu Jiang Yan Chao Zhao Dapeng Chen Tianchun Ye Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences China Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences

ISBN: (纸本)9781479904792

In this paper, the Hot-Carrier (HC) degradation characteristics and mechanisms of nMOSFETs with high-k/metal gate (HK/MG) structure are systematically investigated. The Idsat shift under different Vd states obeys power-law of Vg stress time, and the exponent of Vg stress time shifts from 0.5~0.7 at low stress to 0.2~0.3 at high stress, which is believed to be induced by different trap activities. There are two transitions in the curve of time to fail (TTF) and Vg stress, the 1 st valley point is resulted from impact ionization, and the 2 nd transition is attributed to the dominant roles exchange of the interface trap (Nit) and bulk trap (Not) in dielectric in degradation.

关键词： Stress Degradation Impact ionization Failure analysis Integrated circuits Threshold voltage Substrates

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