Unmanned air vehicles (UAVs) are identified as an integral part of future military forces. The coordinated route-planning problems of UAV team with various architectures are addressed in the framework of game theory. ...
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ISBN:
(纸本)0780384032
Unmanned air vehicles (UAVs) are identified as an integral part of future military forces. The coordinated route-planning problems of UAV team with various architectures are addressed in the framework of game theory. A two-stage route planner has been proposed, which combines various game models and the concept of evolutionary computation and is compatible with the cooperative/competitive nature envisioned for UAV team. Our route planner can handle different kinds of mission constraints in hierarchical style. Potential routes of each vehicle form their own sub-population, and evolve only in their own sub-population, while the cooperation and competition among UAVs are reflected by the definition of fitness function. Experimental results show the feasibility of generating the coordinated routes for UAV team using game theory methods.
This paper proposes a novel fast architecture for a 2D discrete wavelet transform by using a lifting scheme, Parallel and embedded decimation techniques are employed to optimize the architecture, which is mainly compo...
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ISBN:
(纸本)078038511X
This paper proposes a novel fast architecture for a 2D discrete wavelet transform by using a lifting scheme, Parallel and embedded decimation techniques are employed to optimize the architecture, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. The architecture is designed to generate two outputs in one working clock cycle, with every two subbands coefficients alternately. The total time for computing J levels of decomposition for an N/spl times/N image is approximately 2N/sup 2/(1-4/sup -J/)/3 clock cycles. In comparison with the other devices reported in previous literature, the design has many advantages including lower hardware complexity and area and power efficiency. The design is also fast, regular and simple, as well as well suited for VLSI implementation.
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