A novel compact model for on-chip stacked transformers is *** proposed model topology gives a clear distinction to the eddy current,resistive and capacitive losses of the primary and secondary coils in the substrate.A...
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A novel compact model for on-chip stacked transformers is *** proposed model topology gives a clear distinction to the eddy current,resistive and capacitive losses of the primary and secondary coils in the substrate.A method to analytically determine the non-ideal parasitics between the primary coil and substrate is *** model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1:1 stacked transformer manufactured in a commercial rf-CMOS technology.
A pulse swallowing frequency divider with low power and compact structure is *** of the DFFs in the divided by 2/3 prescaier is controlled by the modulus control signal,and automatically powered off when it has no con...
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A pulse swallowing frequency divider with low power and compact structure is *** of the DFFs in the divided by 2/3 prescaier is controlled by the modulus control signal,and automatically powered off when it has no contribution to the operation of the *** DFFs in the program counter and the swallow counter are shared to compose a compact structure,which reduces the power consumption *** proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28×22μm;.The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.
A meminductor is a new type of memory device developed from the *** present a mathematical model of a flux-controlled meminductor and its equivalent circuit model for exploring the properties of the meminductor in a n...
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A meminductor is a new type of memory device developed from the *** present a mathematical model of a flux-controlled meminductor and its equivalent circuit model for exploring the properties of the meminductor in a nonlinear *** explore the response characteristics of the meminductor under the exciting signals of sinusoidal,square,and triangular waves by using theoretical analysis and experimental tests,and design a meminductor-based oscillator based on the *** analysis and experiments show that the meminductor-based oscillator possesses complex bifurcation behaviors and can generate periodic and chaotic oscillations.A special phenomenon called the co-existent oscillation that can generate multiple oscillations(such as chaotic,periodic oscillations as well as stable equilibrium) with the same parameters and different initial conditions *** also design an analog circuit to realize the meminductor-based oscillator,and the circuit experiment results are in accordance with the theory analysis.
A memcapacitor is a new type of memory capacitor. Before the advent of practical memcapacitor, the prospective studies on its models and potential applications are of importance. For this purpose, we establish a mathe...
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A memcapacitor is a new type of memory capacitor. Before the advent of practical memcapacitor, the prospective studies on its models and potential applications are of importance. For this purpose, we establish a mathematical memca- pacitor model and a corresponding circuit model. As a potential application, based on the model, a memcapacitor oscillator is designed, with its basic dynamic characteristics analyzed theoretically and experimentally. Some circuit variables such as charge, flux, and integral of charge, which are difficult to measure, are observed and measured via simulations and exper- iments. Analysis results show that besides the typical period-doubling bifurcations and period-3 windows, sustained chaos with constant Lyapunov exponents occurs. Moreover, this oscillator also exhibits abrupt chaos and some novel bifurcations. In addition, based on the digital signal processing (DSP) technology, a scheme of digitally realizing this memcapacitor os- cillator is provided. Then the statistical properties of the chaotic sequences generated from the oscillator are tested by using the test suit of the National Institute of Standards and Technology (NIST). The tested randomness definitely reaches the standards of NIST, and is better than that of the well-known Lorenz system.
A novel MEMS inertial sensor with enhanced sensing capacitors is developed. The designed fabricated process of the sensor is a deep RIE process, which can increase the mass of the seismic to reduce the mechanical nois...
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A novel MEMS inertial sensor with enhanced sensing capacitors is developed. The designed fabricated process of the sensor is a deep RIE process, which can increase the mass of the seismic to reduce the mechanical noise, and the designed capacitance sensing method is changing the capacitance area, which can reduce the air damping between the sensing capacitor plates and reduce the requirement for the DRIE process precision, and reduce the electronic noise by increasing the sensing voltage to improve the resolution. The design and simulation are also verified by using the FEM tool ANSYS. The simulated results show that the transverse sensitivity of the sensor is approximately equal to zero. Finally, the fabricated process based on silicon-glass bonding and the preliminary test results of the device for testing grid capacitors and the novel inertial sensor are presented. The testing quality factor of the testing device based on the slide-film damping effect is 514, which shows that the enhanced capacitors can reduce mechanical noise. The preliminary testing result of the sensitivity is 0.492pf/g.
Deviation of threshold voltage and effective mobility due to random dopant fluctuation is *** improved 65 nm average drain current MOS model calledαlaw is utilized after fitting HSPICE simulating data and extracting ...
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Deviation of threshold voltage and effective mobility due to random dopant fluctuation is *** improved 65 nm average drain current MOS model calledαlaw is utilized after fitting HSPICE simulating data and extracting process ***,a current mismatch model of nanoscale MOSFETs induced by random dopant fluctuation is presented based on propagation of variation *** test conditions,the calculated standard deviation applying this model,compared to 100 times Monte-Carlo simulation data with HSPICE,indicates that the average relative error and relative standard deviation is 0.24%and 0.22%,*** results show that this mismatch model is effective to illustrate the physical mechanism,as well as being simple and accurate.
This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP ch...
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This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong *** simulation convergence is greatly improved by this *** original scheme is developed to extract the parameters of the PSP charge model based on S-parameters *** interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector *** model is verified with an LC VCO design,and exhibits excellent convergence during *** results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(rf) circuit design.
A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS *** employs a wideband LC voltage-controlled oscillator(VCO) with optimized VCO gain(KVCO/and a sub-band step to improve automatic freque...
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A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS *** employs a wideband LC voltage-controlled oscillator(VCO) with optimized VCO gain(KVCO/and a sub-band step to improve automatic frequency calibration(AFC) efficiency at negligible expense of phase noise *** agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth *** results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant *** frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.
An improved large signal model for InP HEMTs is proposed in this *** channel current and charge model equations are constructed based on the Angelov model *** the equations for channel current and gate charge models w...
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An improved large signal model for InP HEMTs is proposed in this *** channel current and charge model equations are constructed based on the Angelov model *** the equations for channel current and gate charge models were all continuous and high order drivable,and the proposed gate charge model satisfied the charge *** the strong leakage induced barrier reduction effect of InP HEMTs,the Angelov current model equations are *** channel current model could fit DC performance of devices.A 2×25μm×70 nm InP HEMT device is used to demonstrate the extraction and validation of the model,in which the model has predicted the DC I–V,C–V and bias related S parameters accurately.
This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of rf CMOS technology. Compared with a standard multi-finger device with uniform gate-fin...
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This paper investigates the effect of a non-uniform gate-finger spacing layout structure on the avalanche breakdown performance of rf CMOS technology. Compared with a standard multi-finger device with uniform gate-finger spacing, a device with non-uniform gate-finger spacing represents an improvement of 8.5% for the drain-source breakdown voltage (BVds) and of 20% for the thermally-related drain conductance. A novel compact model is proposed to accurately predict the variation of BVds with the total area of devices, which is dependent on the different finger spacing sizes. The model is verified and validated by the excellent match between the measured and simulated avalanche breakdown characteristics for a set of uniform and non-uniform gate-finger spacing arranged nMOSFETs.
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