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Double-πfully scalable model for on-chip spiral inductors

Journal of Semiconductors 2012年第8期33卷 71-81页

作者：刘军钟琳王皇艾进才孙玲玲余志平 Marissa Condon Key Laboratory of RF Circuits and Systems Ministry of EducationHangzhou Dianzi University School of Electronic Engineering Dublin City University

A novel double-n equivalent circuit model for on-chip spiral inductors is presented. A hierarchical structure, similar to that of MOS models is introduced. This enables a strict partition of the geometry scaling in the global model and the model equations in the local model. The major parasitic effects, including the skin effect, the proximity effect, the inductive and capacitive loss in the substrate, and the distributed effect, are analytically calculated with geometric and process parameters in the locaMevel. As accurate values of the layout and process parameters are difficult to obtain, a set of model parameters is introduced to correct the errors caused by using these given inaccurate layout and process parameters at the local level. Scaling rules are defined to enable the formation of models that describe the behavior of the inductors of a variety of geometric dimensions. A series of asymmetric inductors with different geometries are fabricated on a standard 0.18-μm SiGe BiCMOS process with 100 Ω/cm substrate resistivity to verify the proposed model. Excellent agreement has been obtained between the measured results and the proposed model over a wide frequency range.

关键词： spiral inductor double-x equivalent circuit fully scalable

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A surface-potential-based model for AlGaN/AlN/GaN HEMT

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Journal of Semiconductors 2013年第9期34卷 41-44页

作者：汪洁孙玲玲刘军周明珠 Department of Electrical Engineering Zhejiang University Key Laboratory of RF Circuits and Systems Ministry of EducationHangzhou Dianzi University

A new surface-potential-based model for A1GaN/A1N/GaN high electron mobility transistor （HEMT） is proposed in this paper. Since the high polarization effects caused by AlN interlayer favorably influence the two dimensional electron gas （2DEG） and scattering mechanisms, we first add spontaneous and piezoelectric charge terms to the source equation of surface-potential, and a mobility model for A1GaN/A1N/GaN HEMT is rewritten. Compared with TCAD simulations, the DC characteristics of A1GaN/AIN/GaN HEMT are faithfully reproduced by the new model.

关键词： A1GaN/A1N/GaN HEMT 2DEG surface potential polarization effects mobility

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A Three Stage, Fully Differential D-band CMOS Power Amplifier 13

A Three Stage, Fully Differential D-band CMOS Power Amplifie...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Xianghong Gao Lingling Sun Jincai Wen Guodong Su Meng Jin Jiawu Zhou Key Laboratory of RF Circuits and Systems Ministry of EducationHangzhou Dianzi University

ISBN: (纸本)9781467397209

In this paper, the design and implementation of a three stage fully differential D-band power amplifier in 65 nm CMOS technology is demonstrated. By using the capacitive neutralization technology and inter-stage matching networks based on transformers, this power amplifier achieves a peak power gain of 16.8d B and7.9dB m saturated output power at 140 GHz. The power amplifier occupies 0.2mm chip area(including pads).And the power consumption is 80 mW from a 1.2V supply voltage(2V for the cascode stage).

关键词： D-band CMOS power amplifier neutralization gain

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Ultra-low temperature radio-frequency performance of partially depleted silicon-on-insulator n-type metal-oxide-semiconductor field-effect transistors with tunnel diode body contact structures

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Chinese Physics B 2016年第11期25卷 652-655页

作者：吕凯陈静黄瑜萍刘军罗杰馨王曦 State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Microsystem and Information Technology University of Chinese Academy of Sciences Key Laboratory for RF Circuits and Systems of Ministry of Education Hangzhou Dianzi University

Radio-frequency（rf） characteristics under ultra-low temperature of multi-finger partially depleted silicon-oninsulator（PD SOI） n-type metal-oxide-semiconductor field-effect transistors（nMOSFETs） with tunnel diode body-contact（TDBC） structure and T-gate body-contact（TB） structure are investigated in this *** operating at 77 K,TDBC device suppresses floating-body effect（FBE） as well as the TB *** TB device and TDBC device,cut-off frequency（fT） improves as the temperature decreases to liquid-helium temperature（77 K） while that of the maximum oscillation frequency（/max） is opposite due to the decrease of the unilateral power *** operating under 77 K,fT and f（max） of TDBC device reach to 125 GHz and 77 GHz,representing 8%and 15% improvements compared with those of TB device,respectively,which is mainly due to the lower parasitic resistances and *** results indicate that TDBC SOI MOSFETs could be considered as promising candidates for analog and rf applications over a wide range of temperatures and there is immense potential for the development of rf CMOS integrated circuits for cryogenic applications.

关键词： depleted immense representing tunnel partially finger floating analog helium insulator

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Darwin:a neuromorphic hardware co-processor based on Spiking Neural Networks

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Science China(Information Sciences) 2016年第2期59卷 232-236页

作者： Juncheng SHEN De MA Zonghua GU Ming ZHANG Xiaolei ZHU Xiaoqiang XU Qi XU Yangjing SHEN Gang PAN College of Computer Science Zhejiang University Institute of VLSI Design Zhejiang University Key Laboratory of RF Circuits and Systems Ministry of Education Hangzhou Dianzi University

Broadly speaking, the goal of neuromorphic engineering is to build computer systems that mimic the brain. Spiking Neural Network(SNN) is a type of biologically-inspired neural networks that perform information processing based on discrete-time spikes, different from traditional Artificial Neural Network(ANN).Hardware implementation of SNNs is necessary for achieving high-performance and low-power. We present the Darwin Neural Processing Unit(NPU), a neuromorphic hardware co-processor based on SNN implemented with digitallogic, supporting a maximum of 2048 neurons, 20482= 4194304 synapses, and 15 possible synaptic *** Darwin NPU was fabricated by standard 180 nm CMOS technology with an area size of 5 × 5 mm2and70 MHz clock frequency at the worst case. It consumes 0.84 m W/MHz with 1.8 V power supply for typical applications. Two prototype applications are used to demonstrate the performance and efficiency of the hardware implementation.

关键词： neuromorphic computing Spiking Neural Networks(SNN) digital VLSI

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A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

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Chinese Physics B 2022年第7期31卷 629-636页

作者： Pei Shen Ying Wang Fei Cao The Key Laboratory of RF Circuits and Systems Ministry of EducationHangzhou Dianzi UniversityHangzhou 310018China The School of Mechanical and Electronic Engineering Pingxiang UniversityPingxiang 337055China

An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD *** optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the *** improved structure is named as *** side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state *** wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.

关键词： 4H-silicon carbide(4H-SiC)trench gate MOSFET breakdown voltage(V_(BR)) specific onresistance(R_(on sp)) switching energy loss super-junction

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Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution

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Chinese Physics B 2016年第7期25卷 164-170页

作者：张钰逯鑫淼王光义胡永才徐江涛 Key Laboratory for RF Circuits and Systems (Hangzhou Dianzi University) Ministry of Education Institute of Electronics and Information Hangzhou Dianzi University School of Electronics and Information Engineering Tianjin University

The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result,the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated,and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.

关键词： random telegraph signal noise physical and statistical model binomial distribution CMOS image sensor

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Improved 4H-SiC UMOSFET with super-junction shield region

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Chinese Physics B 2021年第5期30卷 694-700页

作者： Pei Shen Ying Wang Xing-Ji Li Jian-Qun Yang Cheng-Hao Yu Fei Cao Key Laboratory of RF Circuits and Systems Ministry of EducationHangzhou Dianzi UniversityHangzhou 310018China National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment Harbin Institute of TechnologyHarbin 150080China

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded *** modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the *** n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same *** p-type conductive pillars relieve the electric field(E-field)in the corner of the trench ***-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy *** advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted *** the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.

关键词： breakdown voltage specific on-resistance silicon carbide switching energy loss super-junction(SJ) trench gate MOSFET

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Simulation study of high voltage GaN MISFETs with embedded PN junction

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Chinese Physics B 2020年第8期29卷 198-203页

作者： Xin-Xing Fei Ying Wang Xin Luo Cheng-Hao Yu College of Information and Communication Engineering Harbin Engineering UniversityHarbin 150001China Key Laboratory of RF Circuits and Systems Ministry of EducationHangzhou Dianzi UniversityHangzhou 310018China

In this paper,we propose a new enhanced GaN MISFET with embedded pn junction,i.e.,EJ-MISFET,to enhance the breakdown *** embedded pn junction is used to improve the simulated device electric field distribution between gate and drain,thus achieving an enhanced breakdown voltage(BV).The proposed simulated device with LGD=15μm presents an excellent breakdown voltage of 2050 V,which is attributed to the improvement of the device electric field distribution between gate and *** addition,the ON-resistance(RON)of 15.37Ω·mm and Baliga's figure of merit of 2.734 GW·cm-2 are achieved in the optimized *** with the field plate conventional GaN MISFET(FPC-MISFET)without embedded pn junction structure,the proposed simulated device increases the BV by 32.54%and the Baliga's figure of merit is enhanced by 71.3%.

关键词： TCAD Baliga’s figure of merit(BFOM) breakdown voltage(BV)

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A Real-time Waveform Load-Pull Technique Enabling the Access to rf PA Ruggedness

A Real-time Waveform Load-Pull Technique Enabling the Access...

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2021 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2021

作者： Zhao, Siyuan Pan, Tao Su, Jiangtao Ministry of Education Key Laboratory of Rf Circuits and Systems Hangzhou310018 China

ISBN: (纸本)9781665418287

Load mismatch becomes an urgent issue to be resolved in the design of rf PA circuit with the fast development of wireless communication technology. In this paper, we proposed a real-time waveform load pull technique for rf PA ruggedness test, which can be used for both fundamental and harmonic load mismatch and deliver accurate output waveforms. This technique has many advantages versus traditional passive load pull based techniques. Through rigorous experimental verification, it is proved that this technique is capable of providing comprehensive and meaningful information for the rf circuit Electro-Magnetic safety analysis and design. © 2021 IEEE.

关键词： Electro-Magnetic Load mismatch Load Pull Output Waveforms rf PA

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