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International Conference on Software Analysis, Testing and Evolution (SATE)

作者： Yongang Che Chuanfu Xu Zhenghua Wang Computer College National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory (PDL) National University of Defense Technology Changsha China

ISBN: (纸本)9781509045181

Powering is an important operation in many computation intensive workloads. This paper investigates the performance of different styles to calculate the powering operations from the application level. A series of small benchmark codes that calculate the powering operations in different ways are designed. Their performance is evaluated on Intel Xeon CPU under Intel compilation environments. The results show that the number of floating-point operations and the related runtime are sensitive to the value of the exponent Y and how it is used. When Y is an immediate integer number whose value is known at compile time, the cost of powering is much less than the situation when Y is an integer variable whose value is known at runtime. When Y is defined as a real variable, the cost of powering is always high, be it equals to an integer number or not. Based on the investigations, performance optimizations are applied to a kernel subroutine from a real-world supersonic combustion simulation code, which intensively involves powering operations. The result shows that the performance of that subroutine is improved for 13.25 times on the Intel Xeon E5-2692 CPU.

关键词： Benchmark testing Arrays Libraries Runtime Signal processing algorithms Hardware

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Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Ve...

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IEEE Computer Society Annual Symposium on VLSI

作者： Sheng Liu Hanyan Chen Jianghua Wan Yaohua Wang College of Computer National University of Defense Technology Changsha Hunan China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467390408

Binary Exchange Algorithm (BEA) always introduces excessive shuffle operations when mapping FFTs on vector SIMD DSPs. This can greatly restrict the overall performance. We propose a novel mod (2P-1) shuffle function and Mod-BEA algorithm (MBEA), which can halve the shuffle operation count and unify the shuffle mode. Such unified shuffle mode inspires us to propose a set of novel mod (2P-1) shuffle memory-access instructions, which can totally eliminate the shuffle operations. Experimental results show that the combination of MBEA and the proposed instructions can bring 17.2%-31.4% performance improvements at reasonable hardware cost, and compress the code size by about 30%.

关键词： Digital signal processing Hardware Pipelines Computer architecture Linearity Computers Software

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Efficient detection of dangling pointer error for C/C++ programs

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Journal of Physics: Conference Series 2017年第1期887卷

作者： Wenzhe Zhang Science and Technology on Parallel and Distributed Laboratory State Key Laboratory of High Performance Computing State Key Laboratory of High-end Server & Storage Technology College of Computer National University of Defense Technology Changsha PR China

Dangling pointer error is pervasive in C/C++ programs and it is very hard to detect. This paper introduces an efficient detector to detect dangling pointer error in C/C++ programs. By selectively leave some memory accesses unmonitored, our method could reduce the memory monitoring overhead and thus achieves better performance over previous methods. Experiments show that our method could achieve an average speed up of 9% over previous compiler instrumentation based method and more than 50% over previous page protection based method.

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High Performance Interconnect Network for Tianhe System

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Journal of Computer science & technology 2015年第2期30卷 259-272页

作者：廖湘科庞征王克非卢宇彤谢旻夏军董德尊所光 College of Computer National University of Defense Technology Changsha 410073 Science and Technology on Parallel and Distributed Processing Laboratory National Changsha 410073 China China University of Defense Technology State Key Laboratory of High Performance Computing National University of Defense Technology Changsha 410073 China

In this paper, we present the Tianhe-2 interconnect network and message passing services. We describe the architecture of the router and network interface chips, and highlight a set of hardware and software features effectively supporting high performance communications, ranging over remote direct memory access, collective optimization, hardwareenable reliable end-to-end communication, user-level message passing services, etc. Measured hardware performance results are also presented.

关键词： Tianhe-2 supercomputer interconnect network router architecture network interface architecture user-level message passing

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EmSBoT: A lightweight modular software framework for networked robotic systems

EmSBoT: A lightweight modular software framework for network...

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International Conference on Advances in Computational Tools for Engineering Applications, ACTEA

作者： Long Peng Fei Guan Luc Perneel Hasan Fayyad-Kazan Martin Timmerman Department of Electronics and Informatics Vrije Universiteit Brussel (VUB) Brussel-Belgium National Key Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781467385244

Developing applications for modern complex networked robotic systems is more challenging due to the introduction of possibly sophisticated communication and coordination aspects. In this paper, we propose EmSBoT, a lightweight embedded component-based software framework targeting resource-constrained networked robotic systems. EmSBoT provides a unified Application Program Interface (API) that hides the heterogeneous distributed environment from applications. Its OS abstraction layer endows it with OS independence and portability. A port-based communication mechanism is adopted to exchange message between loosely coupled components, making the system with fault-tolerance capability. By isolating the communication channels as separate agents, the framework provides uniform and transparent message-passing for agents over node boundaries. We describe the architecture, programming model and core features of EmSBoT in this paper, together with the performance evaluation and behavior validation to demonstrate its efficiency and feasibility.

关键词： Ports (Computers) Robot kinematics Real-time systems Programming Operating systems

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Towards Robust Ego-Centric Hand Gesture Analysis for Robot Control

Towards Robust Ego-Centric Hand Gesture Analysis for Robot C...

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2016 IEEE International Conference on Signal and Image processing

作者： Hongyong Song Weijiang Feng Naiyang Guan Xuhui Huang Zhigang Luo Institute of Software College of Computer National University of Defense Technology Department of Computer Science and Technology College of Computer National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology

Wearable device with an ego-centric camera would be the next generation device for human-computer interaction such as robot *** gesture is a natural way of egocentric human-computer *** this paper, we present an ego-centric multi-stage hand gesture analysis pipeline for robot control which works robustly in the unconstrained environment with varying *** particular, we first propose an adaptive color and contour based hand segmentation method to segment hand region from the egocentric *** then propose a convex U-shaped curve detection algorithm to precisely detect positions of *** parallelly, we utilize the convolutional neural networks to recognize hand *** on these techniques, we combine most information of hand to control the robot and develop a hand gesture analysis system on an i Phone and a robot arm platform to validate its *** result demonstrates that our method works perfectly on controlling the robot arm by hand gesture in real time.

关键词： ego-centric vision hand detection and segmentation fingertips detection hand gesture recognition robot control human-computer interaction

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Maximizing Uniform Multicast Throughput in Multi-Channel Dense Wireless Sensor Networks 12

Maximizing Uniform Multicast Throughput in Multi-Channel Den...

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12th International Conference on Mobile Ad-Hoc and Sensor Networks, MSN 2016

作者： Jiao, Xianlong Chen, Guirong Wang, Xiaodong Chen, Yuli Yang, Li Information and Navigation College Air Force Engineering University Xi'an710077 China College of Information System and Management National University of Defense Technology Changsha410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China Chongqing Guanyinqiao Elementary School Chongqing400020 China Chongqing Liangjiangxinqu Renhe Experimental School Chongqing400021 China

ISBN: (纸本)9781509056965

This paper investigates the problem of maximizing uniform multicast throughput (MUMT) for multi-channel dense wireless sensor networks, where all nodes locate within one-hop transmission range and can communicate with each other on multiple orthogonal channels. This kind of networks show wide application in the real world, and maximizing uniform multicast throughput for these networks is worth deep studying. Previous researches have proved MUMT problem is NP-hard. However, previous researches are either hard to implement, or use too many relay nodes to complete the multicast task, and thus incur high overhead or poor performance. To efficiently solve MUMT problem, we adopt the concept of the maximum independent set with the size constraint, and present one novel Single-Broadcast based Multicast algorithm called SBM based on the concept. We prove that SBM algorithm achieves a constant ratio to the theoretical throughput upper bound. Extensive experimental results demonstrate that, SBM performs better than existing work in terms of both the uniform multicast throughput and the total number of transmissions. © 2016 IEEE.

关键词： Throughput

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DIPP—An LLC replacement policy for on-chip dynamic heterogeneous multi-core architecture

DIPP—An LLC replacement policy for on-chip dynamic heteroge...

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International Conference of Young Computer Scientists, Engineers and Educators, ICYCSEE 2015

作者： Yang, Zhang Zuocheng, Xing Xiao, Ma Science and technology on Parallel and distributed processing laboratory National University of Defense Technology ChangSha China

ISBN: (纸本)9783662462478

As the big data era is coming, it brings new challenges to the massive data processing. A combination of GPU and CPU on chip is the trend to release the pressure of large scale computing. We found that there are different memory access characteristics between GPU and CPU. The most important one is that the programs of GPU include a large number of threads, which lead to higher access frequency in cache than the CPU programs. Although the LRU policy favors the programs with high memory access frequency, the programs of GPU can’t get the corresponding performance boost even more cache resources are provided. So LRU policy is not suitable for heterogeneous multi-core processor. Based on the different characteristics of GPU and CPU programs on memory access, this paper proposes an LLC dynamic replacement policy--DIPP (Dynamic Insertion/ Promotion Policy) for heterogeneous multi-core processors. The core idea of the replacement policy is to reduce the miss rate of the program and enhance the overall system performance by limiting the cache resources that GPU can acquire and reducing the thread interferences between programs. Experiments compare the DIPP replacement policy with LRU and we conduct a classified discussion according to the program results of GPU. Friendly programs enhance 23.29% on the average performance (using arithmetic mean). Large working sets programs can improve 13.95%, compute-intensive programs enhance 9.66% and stream class programs improve 3.8%. © Springer-Verlag Berlin Heidelberg 2015.

关键词： Graphics processing unit

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Enhancing Temporal Alignment with Autoencoder Regularization

Enhancing Temporal Alignment with Autoencoder Regularization

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International Joint Conference on Neural Networks

作者： Liquan Nie Yuanyuan Wang Xiang Zhang Xuhui Huang Zhigang Luo Science and Technology on Parallel and Distributed Processing Laboratory College of Computer National University of Defense Technology Department of Basic Courses Army Officer Academy Department of Computer Science and Technology College of Computer National University of Defense Technology

ISBN: (纸本)9781509006212

Temporal alignment aligns two temporal sequences and is quite challenging due to drastic differences among temporal sequences and source data from different views. Canonical time warping (CTW) has shown great potential in temporal alignment tasks because it can reduce data redundancy by transforming high-dimensional data to a lower-dimensional subspace via canonical correlation analysis (CCA). However, CTW cannot uncover the underlying nonlinear structure embedded in the dataset. In this paper, we propose an autoencoder regularized canonical time warping method (AECTW) to overcome this drawback. Specifically, AECTW enhances lower-dimensional representation of each sequence by incorporating an autoencoder regularization, meanwhile reveals the nonlinear structure of features by explicit nonlinear transformation. By these strategies, AECTW significantly boosts CTW in temporal alignment tasks. Experiments on both synthetic data and two practical human action datasets demonstrate that AECTW outperforms the representative DTW-based methods.

关键词： NONLINEAR STRUCTURES data redundancy Dataset synthetic data Alignment Warping Structural properties Canonical Religious Missions Data sources

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Improving performance portability for GPU-specific Open CL kernels on multi-core/many-core CPUs by analysis-based transformations

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Frontiers of Information technology & Electronic Engineering 2015年第11期16卷 899-916页

作者： Mei WEN Da-fei HUANG Chang-qing XUN Dong CHEN School of Computer National University of Defense Technology National Key Laboratory of Parallel and Distributed Processing

OpenCL is an open heterogeneous programming framework. Although OpenCL programs are func- tionally portable, they do not provide performance portability, so code transformation often plays an irreplaceable role. When adapting GPU-specific OpenCL kernels to run on multi-core/many-core CPUs, coarsening the thread granularity is necessary and thus has been extensively used. However, locality concerns exposed in GPU-specific OpenCL code are usually inherited without analysis, which may give side-effects on the CPU performance. Typi- cally, the use of OpenCL＇s local memory on multi-core/many-core CPUs may lead to an opposite performance effect, because local-memory arrays no longer match well with the hardware and the associated synchronizations are costly. To solve this dilemma, we actively analyze the memory access patterns using array-access descriptors derived from GPU-specific kernels, which can thus be adapted for CPUs by （1） removing all the unwanted local-memory arrays together with the obsolete barrier statements and （2） optimizing the coalesced kernel code with vectorization and locality re-exploitation. Moreover, we have developed an automated tool chain that makes this transformation of GPU-specific OpenCL kernels into a CPU-friendly form, which is accompanied with a scheduler that forms a new OpenCL runtime. Experiments show that the automated transformation can improve OpenCL kernel performance on a multi-core CPU by an average factor of 3.24. Satisfactory performance improvements axe also achieved on Intel＇s many-integrated-core coprocessor. The resultant performance on both architectures is better than or comparable with the corresponding OpenMP performance.

关键词： OpenCL Performance portability Multi-core/many-core CPU Analysis-based transformation

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