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M-IVC: Using multiple input vectors to minimize aging-induced delay

M-IVC: Using multiple input vectors to minimize aging-induce...

引用

18th Asian Test Symposium, ATS 2009

作者： Jin, Song Han, Yinhe Zhang, Lei Li, Huawei Li, Xiaowei Yan, Guihai Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Graduate University Beijing China

ISBN: (纸本)9780769538648

Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit performance. NBTI degradation has strong dependence on input pattern and duty cycles. Based on this observation, we propose to apply multiple input vectors to the combination circuit in a non-uniform way during standby mode. Multiple input vectors can enhance the capability to control the circuit nodes, achieve smaller duty cycles to reduce the stress time of gates and thus mitigate static NBTI. A constrained multi-object optimization model is formalized to find the optimal combination of duty cycles for timing-critical paths, which in turn minimizes the increase of path delay. An ATPG-like procedure is then presented to generate the corresponding input vectors. Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors. © 2009 IEEE.

关键词： Negative bias temperature instability

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Discretized Gaussian Mixture Hyperprior for Learned Image Compression with Mask Module

Discretized Gaussian Mixture Hyperprior for Learned Image Co...

引用

2022 IEEE International Conference on Multimedia and Expo, ICME 2022

作者： Wang, Shengkai Wang, Hanli Tongji University Department of Computer Science and Technology Shanghai China Tongji University Key Laboratory of Embedded System and Service Computing Ministry of Education Shanghai China

ISBN: (数字)9781665485630

ISBN: (纸本)9781665485630

Learned image compression approaches have shown great potential with promising results. However, according to the commonly used measurement methods, there still lies a performance gap between learned compression methods and the latest compression standard versatile video coding (VVC), because of the remaining redundancy existing in contemporary algorithms. To obtain a more accurate entropy model for rate estimation, discretized Gaussian mixture hyperprior is proposed in this work to parameterize the distribution of latent codes. In addition, a proposed mask module is exploited to enhance the feature extraction ability of the encoder and adaptively allocate bit rates. In this case, the proposed learned image compression model achieves the state-of-the-art performance among the existing learned compression methods and most compression standards on both Kodak24 and CLIC Mobile Validation datasets. The proposed model also outperforms VVC under several bitrate scenarios. © 2022 IEEE.

关键词： Image compression

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Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

引用

2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Hu, Yu Fu, Xiang Fan, Xiaoxin Fujiwara, Hideo Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China 8916-5 Takayama Ikoma Nara 630-0192 Japan

ISBN: (纸本)9781424419227

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead. ©2008 IEEE.

关键词： Multiplexing equipment

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Address remapping for static NUCA in noc-based degradable chip-multiprocessors

Address remapping for static NUCA in noc-based degradable ch...

引用

16th IEEE Pacific Rim International Symposium on Dependable computing, PRDC 2010

作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542898

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme. © 2010 IEEE.

关键词： Network-on-chip

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RAPn: Network Attack Prediction Using Ranking Access Petri Net

RAPn: Network Attack Prediction Using Ranking Access Petri N...

引用

ChinaGrid Annual Conference (ChinaGrid)

作者： Moussa Djiriba Traore Hai Jin Deqing Zou Weizhong Qiang Guofu Xiang Services Computing Technology and System Laboratory Cluster and Grid Computing Laboratory Huazhong University of Science and Technology Wuhan China

Exploits sequencing is a typical way by which an attacker breaks into a network. In such a scenario, each exploit lays as an atomic proposition for subsequent exploits. An attack path is seen as a succession of exploits which take an attacker right to his/her final goal. The set of all possible attack paths form an attack graph. Researchers have proposed a multitude of techniques to generate attack graph which grows exponentially in the size of the network. Hence it is preferable to optimize the choice of solutions which avoid the cost of scalability and cumbersome. In this paper, we propose a comprehensive approach to network vulnerability analysis by ranking access Petri net graph and utilizing a penetration tester's perspective of maximal level of access possible on a host. Our approach has the following benefits: it provides a simple model in which an analyst can work, its algorithmic complexity is polynomial in the size of the network, and has the ability of scaling well to large size networks. Nevertheless, it has some drawback as in place of all possible attack paths, we seek only good attack paths. An analyst may make suboptimal choices when repairing the network.

关键词： Mathematical model Analytical models Databases Finite element methods Automata Permission

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Towards Privacy Preserving Mining over Distributed Cloud Databases

Towards Privacy Preserving Mining over Distributed Cloud Dat...

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International Conference on Cloud and Green computing (CGC)

作者： Ayad Ibrahim Hai Jin Ali A. Yassin Deqing Zou Cluster and Grid Computing Laboratory Services Computing Technology and System Laboratory Huazhong University of Science and Technology Wuhan China

Due to great advances in computing and Internet technologies, organizations have been enabled to collect and generate a large amount of data. Most of these organizations tend to analyze their data to discover new patterns. Usually, analyzing such amount of data requires huge computational power and storage facilities that may not be available to these organizations. Cloud computing offers the best way to solve this problem. Storing the private data of different organizations in the same cloud server enhances the mining process, but at the same time, raises privacy concerns. Therefore, it is highly recommended to support privacy preserving data mining algorithms in the cloud environment. This paper introduces an efficient and accurate cryptography-based scheme for mining the cloud data in a secure way without loss of accuracy. Specifically, we address the problem of K-nearest neighbor (KNN) classification over horizontally distributed databases without revealing any unnecessary information. We have utilized the recently developed cryptography primitive, order preserving symmetric encryption (OPSE), to integrate securely the local classifications at a lower cost than the previously presented privacy preserving data mining schemes. Empirical results on real datasets demonstrate that the proposed scheme has similar performance with the naive mining systems in terms of classification accuracy.

关键词： Cryptography Vectors Distributed databases Accuracy Training Data privacy

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Diva: A dataflow programming model and its runtime support in java virtual machine

Diva: A dataflow programming model and its runtime support i...

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13th IEEE Asia-Pacific Computer systems Architecture Conference, ACSAC 2008

作者： Yang, Chen Bin, Fan Lujie, Zhong Chengyong, Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate School of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424426836

Microprocessors have turned to multicore, i.e. multiple processor cores, along with some levels of on-chip caches and interconnection networks, integrated on a singe chip. However, it brings challenges on how to program these processors effectively and efficiently, which is known as the "Programming Wall". This paper proposes a systematic approach to attack the problem. We describe an extension of Java programming language with dataflow paradigm and transactional memory. Our approach alleviates the difficulties of parallel programming by providing a higher level of abstraction and relieving programmers of low-level threading and locking details. We also describe the design of a runtime system to support and optimize for the extension. We have implemented a prototype based on Apache Harmony DRL Virtual Machine. Preliminary experimental results on a 16-core SMP machine show that our approach achieves reasonable scalability and can adapt to the variance of available hardware resources. © 2008 IEEE.

关键词： Parallel programming

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A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

引用

2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Wang, Fei Hu, Yu Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424419227

The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique. ©2008 IEEE.

关键词： Chains

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Design of new hash mapping functions

Design of new hash mapping functions

引用

IEEE 9th International Conference on Computer and Information technology, CIT 2009

作者： Song, Fenglong Liu, Zhiyong Fan, Dongrui Zhang, Junchao Yu, Lei Yuan, Nan Lin, Wei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflictfree. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewedassociative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme. © 2009 IEEE.

关键词： Hash functions

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An EMAIL Based Automated Trust Negotiation Model

An EMAIL Based Automated Trust Negotiation Model

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International Conference on Computational Intelligence and Security

作者： Zhensong Liao Hai Jin Deqing Zou Chisong Li Services Computing Technology and System Laboratory Cluster and Grid Computing Laboratory Huazhong University of Science and Technology Wuhan China

Automated trust negotiation (ATN) is an important means to establish trust between strangers through the exchange of digital credentials and mobile access control policies specifying what combinations of credentials a stranger must submit. While ATN provides a good mechanism to share resources in the open and distributed environments, there still exist some pitfalls. A notable problem is that the negotiation process is easy to be interrupted, which leads the negotiation to failure. Thereto, current protection techniques are somehow complex and heavyweight, which greatly limits ATN's applications. To solve these problems, an Email Based ATN Model (EBAM) is proposed. A credential template and an access control policy template are specified to carry information. All the transmitted messages are encrypted by private keys. The data exchange is realized through the negotiators' emails. A use case is given to show how it works, which proves the model sound and reasonable.

关键词： Cryptography Costs Security Access control Protocols Public key Computational intelligence Computers Grid computing Mobile computing

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