In order to achieve high-luminance and tiny-size organic light-emitting diode (OLED), contact photolithography and vacuum thermal evaporation are adopted to fabricate OLEDs with different ITO masks: glass/ITO/LiF/hole...
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In order to achieve high-luminance and tiny-size organic light-emitting diode (OLED), contact photolithography and vacuum thermal evaporation are adopted to fabricate OLEDs with different ITO masks: glass/ITO/LiF/hole transport layer (HTL, NPD)/light-emitting layer (EML, 0.5-0.6 vol%Rubrene: Alq3)/electron transport layer(ETL, Alq3)/cathode, in which LiF is used as the insulating layer. We obtain a microfine device with a light-emitting area of 45 μm×2 mm and a tiny device with a diameter of 44 μm, which exhibit the maximum current density of 7 A/cm2 and 40 A/cm2, respectively.
The capacitance-voltage (C-V) characteristics of organic light emitting diodes (OLEDs) are studied. The effects of hole-injection layer on the negative capacitance of OLEDs are investigated. The results show that the ...
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The capacitance-voltage (C-V) characteristics of organic light emitting diodes (OLEDs) are studied. The effects of hole-injection layer on the negative capacitance of OLEDs are investigated. The results show that the negative capacitance is closely related to the electric field distribution in organic hetero-layer light emitting devices, and the onset frequency of the negative capacitance increases exponentially with the square root of the applied bias. Compared with the device with thin film hole-injection layer, the device with doped hole-injection layer has a lower driving voltage, while its charge transfer characteristic and the onset voltage of negative capacitance are more dependent on frequency.
Aiming at the time redundancy in the fiat panel display （FPD） imaging process, the paper studied some problems for FPD gray scale controlling based on the fraetal theory, dissertates the construction of the space-ti...
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Aiming at the time redundancy in the fiat panel display （FPD） imaging process, the paper studied some problems for FPD gray scale controlling based on the fraetal theory, dissertates the construction of the space-time mapping topology architecture, the proposition of optimal scanning structure for FPD＇s gray imaging, and the creation of the fractal theoretic model. Then the logic implementation and systemapplication are presented based on the fraetal model of the optimal scan architecture, and the application results achieved target of eliminating time redundancy and increasing the scanning availability. The novel control mode that the fractal scanning IP core described with Verilog language embedded in the FPGA hardware frame can efficiently increase the imaging gray scales and quality in the FPDs scanning controller and speed up the frame frequency of displaysystem.
The fluid dispensing with a controllable method is one of the key technologies in electronic packaging. The the higher accuracy and consistency boosts the emergence of the new fluid dispensing technologies. This paper...
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A compressed sensing （CS） based channel estimation algorithm is proposed in the fast moving environment. A sparse basis expansion channel model in both time and frequency domain is *** are placed according to a nove...
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A compressed sensing （CS） based channel estimation algorithm is proposed in the fast moving environment. A sparse basis expansion channel model in both time and frequency domain is *** are placed according to a novel random unit pilot matrix （RUPM） to measure the delay- Doppler sparse channel. The sparse channels are recovered by an extension group orthogonal matching pursuit （GOMP） algorithm, enjoying the diversity gain from multi-symbol processing. The relatively nonzero channel coefficients are estimated from a very limited number of pilots at a sampling rate significantly below the Nyquist rate. The simulation results show that the new channel estimator can provide a considerable performance improvement for the fast fading channels. Three significant reductions are achieved in the required number of pilots, memory requirements and computational complexity.
According to the human visual sensitivity characteristics to spatial depth changes, this paper studies the just noticeable depth difference (JNDD) of the detail perception. The JNDD model is proposed through derivatio...
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According to the human visual sensitivity characteristics to spatial depth changes, this paper studies the just noticeable depth difference (JNDD) of the detail perception. The JNDD model is proposed through derivation and analysis on a large number of subjective experiments. Then, a trilateral filtering algorithm is presented based on the model to suppress the unperceivable depth details and to minimize the rendering artifacts due to the inaccurate depth estimation. Subjective and objective experimental results prove that the proposed trilateral filtering algorithm for depth map based on JNDD model can smooth the object edges and reduce the edge noise in the synthesized view while reduce the bit rates.
When the traditional pixel patterning process for the OLED-on-Si microdisplay fabricates the pixel anodes in two independent process flows, the anode patterning process based on complementary metal oxide semiconductor...
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When the traditional pixel patterning process for the OLED-on-Si microdisplay fabricates the pixel anodes in two independent process flows, the anode patterning process based on complementary metal oxide semiconductor (CMOS) process is presented to simplify the manufacture process flow and reduce the huge investment cost. The electro-optical performance of the organic light emitting microdisplay with Al serving as the pixel anode material in the general CMOS process is analyzed. A Si chip for the microdisplay backplane with the minimum pixel size of 12 mm×4 mm is developed. The organic lighting material is produced on the silicon chip surface to fabricate the OLED-on-Si microdisplay. The experiment results show that the light intensity is more than 1000 cd/m2 and the current density is more than 0.1 mA/mm2 when Al is used as the pixel anode material and the 5 V voltage is applied to drive the OLED pixel. The electro-optical response is less than 280 ns. These results indicate that it is feasible to develop the OLED-on-Si microdisplay in the conventional CMOS process.
Multi-camera calibration parameters are needed in free-viewpoint video system to obtain virtual viewpoint. Most existing calibration technologies are for single camera and further research is needed for multi-camera c...
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ISBN:
(纸本)9781849195058
Multi-camera calibration parameters are needed in free-viewpoint video system to obtain virtual viewpoint. Most existing calibration technologies are for single camera and further research is needed for multi-camera calibration. A multi-camera calibration method based on 2D plane calibration algorithm combined with stereo vision calibration is proposed in this paper. Camera intrinsic parameters can be obtained using 2D plane calibration algorithm. Through transforming the world coordinate system, the unique extrinsic parameters are got. The validity of the proposed method is verified by experiments.
Micro-pin-fin cooler mounted on the power chip enables the heat removal to meet modern microsystem requirement. Carbon nanotubes （CNTs） have been proven as a potential material for micro-coolers due to the superior ...
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Micro-pin-fin cooler mounted on the power chip enables the heat removal to meet modern microsystem requirement. Carbon nanotubes （CNTs） have been proven as a potential material for micro-coolers due to the superior thermal conductivity, good mechanical property and so forth, and there appear various applications of CNTs in the micro-cooler technology. In the present paper, an analysis of the thermal and hydraulic characteristics of the micro-pin-fin heat sink was conducted, where air was used as the cooling medium and an impinging jet was introduced to enhance the heat transfer. Three-dimension computational fluid dynamics （CFD） simulations were carried out for micro-pin-fin coolers with various parameters, including the pin-fin size and pattern as well as the jet velocity and nozzle diameter. The flow field and thermal properties of the. micro-pin-fin heat sink were obtained, and the heat removal efficiency was evaluated.
A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test an...
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A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark.
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