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GPP-grep: High-speed regular expression processing engine on general purpose processors

GPP-grep: High-speed regular expression processing engine on...

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15th International Symposium on Research in Attacks, Intrusions, and Defenses, RAID 2012

作者： Valgenti, Victor C. Chhugani, Jatin Sun, Yan Satish, Nadathur Kim, Min Sik Kim, Changkyu Dubey, Pradeep School of EECS Washington State University United States Parallel Computing Lab. Intel Corporation United States

ISBN: (纸本)9783642333378

Deep Packet Inspection (DPI) serves as a major tool for Network Intrusion Detection Systems (NIDS) for matching datagram payloads to a set of known patterns that indicate suspicious or malicious behavior. Regular expressions offer rich context for describing these patterns. Unfortunately, large rule sets containing thousands of patterns coupled with high link-speeds leave most regular expression matching methods incapable of matching at real-time without specialized hardware. We present GPP-grep, an NFA-based regular expression processing engine designed for maximum performance on General Purpose Processors. The primary contribution of GPP-grep is the utilization of the data-level parallelism available in modern CPUs to reduce the overhead incurred when tracking multiple states in NFA. In essence, we build and store the NFA in an architecture-friendly manner that exploits locality and then traverse the NFA maximizing the parallelism available and minimizing cache-misses and long-latency memory lookups. GPPgrep demonstrates 24-57x improvement in throughput over standard finite automata techniques on a set of up to 1200 regular-expressions culled from the NIDS Snort, and is within 1.3x of FPGA hardware-based techniques. GPP-grep achieves 2Gbps throughput on a dual-socket commodity CPU system allowing for line-speed evaluation on commodity hardware. © 2012 Springer-Verlag.

关键词： Program processors

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Large-Scale Energy-Efficient Graph Traversal: A Path to Efficient Data-Intensive Supercomputing 12

Large-Scale Energy-Efficient Graph Traversal: A Path to Effi...

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ACM/IEEE International Conference for High Performance computing, Networking, Storage, and Analysis

作者： Nadathur Satish Changkyu Kim Jatin Chhugani Pradeep Dubey Parallel Computing Lab Intel Corporation

ISBN: (纸本)9781467308052

Graph traversal is a widely used algorithm in a variety of fields, including social networks, business analytics, and high-performance computing among others. There has been a push for HPC machines to be rated not just in Petaflops, but also in "GigaTEPS" (billions of traversed edges per second), and the Graph500 benchmark has been established for this purpose. Graph traversal on single nodes has been well studied and optimized on modern CPU architectures. However, current cluster implementations suffer from high latency data communication with large volumes of transfers across nodes, leading to inefficiency in performance and energy consumption. In this work, we show that we can overcome these constraints using a combination of efficient low-overhead data compression techniques to reduce transfer volumes along with latency-hiding techniques. Using an optimized single node graph traversal algorithm [1], our novel cluster optimizations result in over 6.6X performance improvements over state-of-the-art data transfer techniques, and almost an order of magnitude in energy savings. Our resulting implementation of the Graph500 benchmark achieves 115 GigaTEPS on a 320-node/5120 core Intel~? Endeavor cluster with Intel~? Xeon~? processors E5-2670, which matches the second ranked result in the recent November 2011 Graph500 list [2] with about 5.6X fewer nodes~(12). Our cluster optimizations only have a 1.8X overhead in overall performance from the performance of the optimized single-node implementation, and allows for near-linear scaling with number of nodes. Our algorithm on 1024 nodes on Intel~? Xeon~? processor X5670-based systems (with lower per-node performance) for a large multi-Terabyte graph attained 195 GigaTEPS in performance, proving the high scalability of our algorithm. Our per-node performance is the highest in the top 10 of the Nov 2011 Graph500 list.

关键词： HPC high-performance computing among others our algorithm High Performance computing Ganglia Line graph Clusters pushing

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CloudRAMSort: Fast and efficient large-scale distributed RAM sort on shared-nothing cluster 12

CloudRAMSort: Fast and efficient large-scale distributed RAM...

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2012 ACM SIGMOD International Conference on Management of Data, SIGMOD '12

作者： Kim, Changkyu Park, Jongsoo Satish, Nadathur Lee, Hongrae Dubey, Pradeep Chhugani, Jatin Parallel Computing Lab. Intel Labs. Santa Clara CA United States Structured Data Group Google Research Mountain View United States

ISBN: (纸本)9781450312479

Sorting is a fundamental kernel used in many database operations. The total memory available across cloud computers is now sufficient to store even hundreds of terabytes of data in-memory. Applications requiring high-speed data analysis typically use in-memory sorting. The two most important factors in designing a high-speed in-memory sorting system are the single-node sorting performance and inter-node communication. In this paper, we present CloudRAMSort, a fast and efficient system for large-scale distributed sorting on shared-nothing clusters. CloudRAMSort performs multi-node optimizations by carefully overlapping computation with inter-node communication. The system uses a dynamic multi-stage random sampling approach for improved load-balancing between nodes. CloudRAMSort maximizes per-node efficiency by exploiting modern architectural features such as multiple cores and SIMD (Single-Instruction Multiple Data) units. This holistic combination results in the highest performing sorting performance on distributed shared-nothing platforms. CloudRAMSort sorts 1 Terabyte (TB) of data in 4.6 seconds on a 256-node Xeon X5680 cluster called the Intel Endeavor system. CloudRAMSort also performs well on heavily skewed input distributions, sorting 1 TB of data generated using Zipf distribution in less than 5 seconds. We also provide a detailed analytical model that accurately projects (within avg. 7%) the performance of CloudRAMSort with varying tuple sizes and interconnect bandwidths. Our analytical model serves as a useful tool to analyze performance bottlenecks on current systems and project performance with future architectural advances. With architectural trends of increasing number of cores, bandwidth, SIMD width, cache-sizes, and interconnect bandwidth, we believe CloudRAMSort would be the system of choice for distributed sorting of large-scale in-memory data of current and future systems. © 2012 ACM.

关键词： Sorting

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A GPU-based high-throughput image retrieval algorithm 5

A GPU-based high-throughput image retrieval algorithm

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5th Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Zhu, Feiwen Chen, Peng Yang, Donglei Zhang, Weihua Chen, Haibo Zang, Binyu State Key Lab. of ASIC and System Fudan University China Parallel Processing Institute Fudan University China Architecture Key Lab. Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781450312332

With the development of Internet and cloud computing, multimedia data, such as images and videos, has become one of the most common data types being processed. As the scale of multimedia data being still increasing, it is vitally important to efficiently extract useful information from such a huge amount of multimedia data. However, due to the complexity of the core algorithms, multimedia retrieval applications are not only data intensive but also computationally intensive. Therefore, it has been a major challenge to accelerate the processing speed of such applications to satisfy the real-time requirement. As Graphic Processing Unit (GPU) has entered the general-propose computing domain (GPGPU), it has become one of the most popular accelerators for the applications with real-time requirements. In this paper, we parallelize a widely-used image retrieval algorithm called SURF on GPGPU, which is the core algorithm for many video and image retrieval applications. We first analyze the parallelism within SURF to guarantee that there are sufficient tasks being mapped to the large-scale computation resources in GPGPU. We then exploit some inherent GPGPU characteristics, such as 2D memory, to further boost the performance. Finally, we provide some optimization to the cooperation between CPU and GPGPU, which is generally ignored in previous designs. Experimental results show that our parallelization and optimization achieve a throughput of 340.5 frames/s on a NVIDIA GTX295 GPGPU, which is 15X faster than the maximal optimized CPU version. Compared to CUDA SURF, a state-of-the-art parallelization of SURF on GPGPU, our system achieves a speedup by a factor of 2.3X. © 2012 ACM.

关键词： Graphics processing unit

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Billion-Particle SIMD-Friendly Two-Point Correlation on Large-Scale HPC Cluster Systems 12

Billion-Particle SIMD-Friendly Two-Point Correlation on Larg...

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ACM/IEEE International Conference for High Performance computing, Networking, Storage, and Analysis

作者： Jatin Chhugani Changkyu Kim Hemant Shukla Jongsoo Park Pradeep Dubey John Shalf Horst D. Simon Parallel Computing Lab Intel Corporation Lawrence Berkeley National Laboratory

ISBN: (纸本)9781467308052

Two-point Correlation Function (TPCF) is widely used in astronomy to characterize the distribution of matter/energy in the Universe, and help derive the physics that can trace back to the creation of the universe. However, it is prohibitively slow for current sized datasets, and would continue to be a critical bottleneck with the trend of increasing dataset sizes to billions of particles and more, which makes TPCF a compelling benchmark application for future exa-scale architectures. State-of-the-art TPCF implementations do not map well to the underlying SIMD hardware, and also suffer from load-imbalance for large core counts. In this paper, we present a novel SIMD-friendly histogram update algorithm that exploits the spatial locality of histogram updates to achieve near-linear SIMD scaling. We also present a load-balancing scheme that combines domain-specific initial static division of work and dynamic task migration across nodes to effectively balance computation across nodes. Using Zin supercomputer at Lawrence Livermore National laboratory (25,600 cores of Intel? Xeon? E5-2670, each with 256-bit SIMD), we achieve 90% parallel efficiency and 96% SIMD efficiency, and perform TPCF computation on a 1.7 billion particle dataset in 5.3 hours (at least 35×faster than previous approaches). In terms of cost per performance (measured in flops/$), we achieve at least an order-of-magnitude (11.1 ×) higher flops/$ as compared to the best known results [1]. Consequently, we now have line-of-sight to achieving the processing power for correlation computation to process billion+ particles telescopic data.

关键词： TPCF universe trend of increasing dataset sizes Universe single instruction multiple datastream histograms spatial locality Ganglia Lawrence Livermore National laboratory Dataset ASTRONOMY particles arithmetic High Performance computing

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High Performance Non-uniform FFT on Modern X86-based Multi-core Systems

High Performance Non-uniform FFT on Modern X86-based Multi-c...

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International Symposium on parallel and Distributed Processing (IPDPS)

作者： Dhiraj D. Kalamkar Joshua D. Trzaskoz Srinivas Sridharan Mikhail Smelyanskiy Daehyun Kim Armando Manduca Yunhong Shu Matt A. Bernstein Bharat Kaul Pradeep Dubey Parallel Computing Lab Intel Labs Bangalore KA India Mayo Clinic Minnesota Rochester MN US Parallel Computing Laboratory INTEL Research Laboratory Santa Clara CA USA Department of Physiology and Biomedical Engineering Mayo Clinic Rochester MN USA Parallel Computing Lab Intel Labs Santa Clara CA USA Department of Radiology Mayo Clinic Rochester MN USA

The Non-Uniform Fast Fourier Transform (NUFFT) is a generalization of FFT to non-equidistant samples. It has many applications which vary from medical imaging to radio astronomy to the numerical solution of partial differential equations. Despite recent advances in speeding up NUFFT on various platforms, its practical applications are still limited, due to its high computational cost, which is significantly dominated by the convolution of a signal between a non-uniform and uniform grids. The computational cost of the NUFFT is particularly detrimental in cases which require fast reconstruction times, such as iterative 3D non-Cartesian MRI reconstruction. We propose novel and highly scalable parallel algorithm for performing NUFFT on x86-based multi-core CPUs. The high performance of our algorithm relies on good SIMD utilization and high parallel efficiency. On convolution, we demonstrate on average 90% SIMD efficiency using SSE, as well up to linear scalability using a quad-socket 40-core Intel(R) Xeon(R) E7-4870 Processors based system. As a result, on dual socket Intel(R) Xeon(R) X5670 based server, our NUFFT implementation is more than 4x faster compared to the best available NUFFT3D implementation, when run on the same hardware. On Intel(R) Xeon(R) E5-2670 processor based server, our NUFFT implementation is 1.5X faster than any published NUFFT implementation today. Such speed improvement opens new usages for NUFFT. For example, iterative multi channel reconstruction of a 240×240×240 image could execute in just over 3 minutes, which is on the same order as contemporary non-iterative (and thus less-accurate) 3D NUFFT-based MRI reconstructions.

关键词： Convolution Kernel Interpolation Magnetic resonance imaging Image reconstruction Hardware Transforms

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An insightful program performance tuning chain for GPU computing

An insightful program performance tuning chain for GPU compu...

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12th International Conference on Algorithms and Architectures for parallel Processing, ICA3PP 2012

作者： Jia, Haipeng Zhang, Yunquan Long, Guoping Yan, Shengen Lab. of Parallel Software and Computational Science Institute of Software Chinese Academy of Sciences China College of Information Science and Engineering Ocean University of China China State Key Laboratory of Computing Science Chinese Academy of Sciences China Graduate University of Chinese Academy of Sciences China

ISBN: (纸本)9783642330773

It is challenging to optimize GPU kernels because this progress requires deep technical knowledge of the underlying hardware. Modern GPU architectures are becoming more and more diversified, which further exacerbates the already difficult problem of performance optimization. This paper presents an insightful performance tuning chain for GPUs. The goal is to help non-expert programmers with limited knowledge of GPU architectures implement high performance GPU kernels directly. We achieve it by providing performance information to identify GPU program performance bottlenecks and decide which optimization methods should be adopted, so as to facilitate the best match between algorithm features and underlying hardware characteristics. To demonstrate the usage of tuning chain, we optimize three representative GPU kernels with different compute intensity: Matrix Transpose, Laplace Transform and Integral on both NVIDIA and AMD GPUs. Experimental results demonstrate that under the guidance of our tuning chain, performance of those kernels achieves 7.8~42.4 times speedup compared to their naïve implementations on both NVIDIA and AMD GPU platforms. © 2012 Springer-Verlag.

关键词： Chains

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Miss-Correlation Folding: Encoding Per-Block Miss Correlations in Compressed DRAM for Data Prefetching

Miss-Correlation Folding: Encoding Per-Block Miss Correlatio...

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IEEE International parallel & Distributed Processing Symposium

作者： Gang Liu Jih-Kwon Peir Victor Lee Department of Computer & Information Science & Eng University of Florida Gainesville FL USA Parallel Computing Lab Intel Labs Intel Corporation Santa Clara CA USA

ISBN: (纸本)9781467309752

Cache misses frequently exhibit repeated streaming behavior, i.e. a sequence of cache misses has a high tendency of being repeated. Correlation-based prefetchers record the missing streams in a history table for accurate prefetching. Saving a large miss history in off-chip DRAM is a practical implementation, but incurs access latency and consumes memory bandwidth which leads to performance degradation. In this paper, we investigate a new data prefetching mechanism based on per-block miss correlation where a miss is correlated with an earlier miss when the two misses are closely encountered both in time and space. The miss correlations are captured dynamically and saved along with the content of the data block using a simple data compression technique. As a result of this novel combination, our scheme provides unbounded correlation history and its prefetch metadata can be fetched together with demand data without incurring additional latency nor consuming any memory bandwidth. Performance evaluations using data-parallel applications demonstrate that prefetchers based on per-block miss correlations can improve IPC by 42-139% with an average of 88% compared to the IPC without prefetching. In comparison with regular stream prefetcher, sampled temporal streaming prefetcher and spatial-temporal memory streaming prefetcher, up to 115%, 99% and 98% IPC improvement can be obtained with an average about 36%, 26% and 27% respectively.

关键词： prefetch data parallel miss correlation compress cache temporal spatial

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P-Tracer: Path-Based Performance Profiling in Cloud computing Systems

P-Tracer: Path-Based Performance Profiling in Cloud Computin...

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IEEE Annual International Computer Software and Applications Conference (COMPSAC)

作者： Haibo Mi Huaimin Wang Hua Cai Yangfan Zhou Michael R. Lyu Zhenbang Chen National Lab for Parallel & Distributed Processing National Univ. of Defense Technology Changsha China Computing Platform Alibaba Cloud Computing Company Hangzhou China Dept. of Computer Science & Engineering The Chinese Univ. of Hong Kong Hong Kong

In large-scale cloud computing systems, the growing scale and complexity of component interactions pose great challenges for operators to understand the characteristics of system performance. Performance profiling has long been proved to be an effective approach to performance analysis; however, existing approaches do not consider two new requirements that emerge in cloud computing systems. First, the efficiency of the profiling becomes of critical concern; second, visual analytics should be utilized to make profiling results more readable. To address the above two issues, in this paper, we present P-Tracer, an online performance profiling approach specifically tailored for large-scale cloud computing systems. P-Tracer constructs a specific search engine that adopts a proactive way to process performance logs and generates particular indices for fast queries; furthermore, PTracer provides users with a suite of web-based interfaces to query statistical information of all kinds of services, which helps them quickly and intuitively understand system behavior. The approach has been successfully applied in Alibaba Cloud computing Inc. to conduct online performance profiling both in production clusters and test clusters. Experience with one real-world case demonstrates that P-Tracer can effectively and efficiently help users conduct performance profiling and localize the primary causes of performance anomalies.

关键词： Cloud computing Instruments Postal services Search engines Shape System performance Production

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PALM: parallel architecture friendly latchfree modifications to B+ trees on manycore processors 37

PALM: Parallel architecture friendly latchfree modifications...

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37th International Conference on Very Large Data Bases, VLDB 2011

作者： Sewall, Jason Chhugani, Jatin Kim, Changkyu Satish, Nadathur Dubey, Pradeep Parallel Computing Lab Intel Corporation United States

Concurrency control on B+ trees is primarily achieved with latches, but serialization and contention can hinder scalability. As core counts on current processors increase, it is imperative to develop scalable latch-free techniques for concurrency control. We present PALM, a novel technique for performing multiple concurrent queries on in-memory B+ trees. PALM is based on the Bulk Synchronous parallel model, which guarantees freedom from deadlocks and race conditions. Input queries are grouped and processed in atomic batches, and work proceeds in stages that preclude contention. Transitions between stages are accomplished with scalable point-to-point communication. PALM exploits dataand thread-level parallelism on modern many-core architectures, and performs 40M1 updates/second on trees with 128M keys, and 128M updates/second on trees with 512K keys on the latest CPU architectures. Our throughput is 2.3X-19X that of state-of-theart concurrent update algorithms on in-memory B+ trees. PALM obtains close to peak throughput at very low response times of less than 350μs, even for large trees. We also evaluate PALM on the Intel® Many Integrated Core (Intel® MIC) architecture, and demonstrate a speedup of 1.5-2.1X for out-of-cache tree sizes on an Intel® Knights Ferry over a pair of Intel® Xeon® processors DP X5680 (Westmere-EP) in a dual-socket configuration. © 2011 VLDB Endowment.

关键词： Concurrency control

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