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22nd IEEE International Symposium on parallel and Distributed Processing with Applications, ISPA 2024

作者： Lin, Moheng Shi, Peichang Fu, Xiang Jiang, Feng Yi, Guodong National University of Defense Technology National Key Laboratory of Parallel and Distributed Computing College of Computer Science Changsha410073 China Xiangjiang Lab Changsha410073 China

ISBN: (纸本)9798331509712

Blockchain technology has been extensively uti-lized in decentralized data-sharing applications, with the immutability of blockchain providing a witness for the circulation of data. However, current blockchain data-sharing solutions still fail to address the simultaneous screening needs of both the sender and receiver with multi-keywords. Without the capability to support bilateral simultaneous filtering, the disclosure of reasons for matching failures could inadvertently expose sensitive user data. Therefore, the challenge lies in enabling ciphertexts with multiple keywords and receivers with multiple interests to achieve mutual and simultaneous matching. Based on the technical foundations of SE (Searchable Encryption), MABE (Multi-Attribute Based Encryption), and polynomial fitting, this paper proposes a scheme called DMSA (Decentralized and Multi-keyword selective Sharing and selective Acquisition). This scheme can satisfy soundness, enabling ciphertexts carrying multiple keywords and receivers representing multiple interests to match each other simultaneously. We conducted a security analysis that confirms the security of DMSA against chosen-plaintext attacks. Our experimental results demonstrate a significant efficiency improvement, with a 67% increase over single-keyword data-sharing schemes and a 16% enhancement compared to the existing multi-keyword data-sharing solution. © 2024 IEEE.

关键词： Ciphertext

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Improving graph partitioning for modern graphs and architectures 5

Improving graph partitioning for modern graphs and architect...

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5th Workshop on Irregular Applications: Architectures and Algorithms, IA3 2015

作者： Lasalle, Dominique Patwary, Md Mostofa Ali Satish, Nadathur Sundaram, Narayanan Dubey, Pradeep Karypis, George Department of Computer Science and Engineering University of Minnesota Minneapolis MN55455 United States Parallel Computing Lab Intel Corporation Santa ClaraCA95054 United States

ISBN: (纸本)9781450340014

Graph partitioning is an important preprocessing step in applications dealing with sparse-irregular data. As such, the ability to efficiently partition a graph in parallel is crucial to the performance of these applications. The number of compute cores in a compute node continues to increase, demanding ever more scalability from shared-memory graph partitioners. In this paper we present algorithmic improvements to the multithreaded graph partitioner mt-Metis. We experimentally evaluate our methods on a 36 core machine, using 20 difierent graphs from a variety of domains. Our improvements decrease the runtime by 1.5-11.7 and improve strong scaling by 82%.

关键词： Graph theory

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Efficient sparse matrix-vector multiplication on x86-based many-core processors 13

Efficient sparse matrix-vector multiplication on x86-based m...

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27th ACM International Conference on Supercomputing, ICS 2013

作者： Liu, Xing Smelyanskiy, Mikhail Chow, Edmond Dubey, Pradeep School of Computational Science and Engineering Georgia Institute of Technology Atlanta GA United States Parallel Computing Lab. Intel Corporation Santa Clara CA United States

ISBN: (纸本)9781450321303

Sparse matrix-vector multiplication (SpMV) is an important kernel in many scientific applications and is known to be memory bandwidth limited. On modern processors with wide SIMD and large numbers of cores, we identify and address several bottlenecks which may limit performance even before memory bandwidth: (a) low SIMD efficiency due to sparsity, (b) overhead due to irregular memory accesses, and (c) load-imbalance due to non-uniform matrix structures. We describe an efficient implementation of SpMV on the Intel® Xeon Phi™ Coprocessor, codenamed Knights Corner (KNC), that addresses the above challenges. Our implementation exploits the salient architectural features of KNC, such as large caches and hardware support for irregular memory accesses. By using a specialized data structure with careful load balancing, we attain performance on average close to 90% of KNC's achievable memory bandwidth on a diverse set of sparse matrices. Furthermore, we demonstrate that our implementation is 3.52x and 1.32x faster, respectively, than the best available implementations on dual Intel® Xeon™ Processor E5-2680 and the NVIDIA Tesla K20X architecture. © 2013 ACM.

关键词： Bandwidth

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Linking stack overflow to issue tracker for issue resolution 2014

Linking stack overflow to issue tracker for issue resolution

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6th Asia-Pacific Symposium on Internetware, Internetware 2014

作者： Wang, Tao Yin, Gang Wang, Huaimin Yang, Cheng Zou, Peng Key Lab. of Parallel and Distributed Computing Colledge of Computer National University of Defence Technology ChangSha Hunan China Academy of Equipment Command and Technology Beijing100000 China

ISBN: (纸本)9781450334013

Issue resolution is a central task for software development. The efficiency of issue fixing largely relies on the issue report quality. Stack Overflow, which hosts rich and real-Time posts about programming-specific problems, is a valuable external source of knowledge for issue resolution. In this paper, we present CrossLink, an analysis framework that automatically introduce related posts in Stack Overflow to issues in Android Issue Tracker. This helps developers to leverage the abundant and professional knowledge from massive programmers in Stack Overflow for issue resolution. CrossLink explores the semantic similarities as well as the temporal associations between the two types of repositories to recommend Stack Overflow posts to Android issues. The internal links in Stack Overflow are also employed to improve the linking accuracy. The experiments prove the effectiveness of CrossLink with precision of 62.51% for top-10 recommendations, which is significantly higher than the state-of-Art method. © 2014 ACM.

关键词： Android (operating system)

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Preserving Utility in Social Network Graph Anonymization

Preserving Utility in Social Network Graph Anonymization

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IEEE International Conference on Trust, Security and Privacy in computing and Communications (TrustCom)

作者： Mohd Izuan Hafez Ninggal Jemal H. Abawajy Parallel and Distributed Computing Lab Deakin University Victoria Australia

To protect from privacy disclosure, the social network graph is modified in order to hide the information that potentially be used to disclose person's identity. However, when the social network graph is changed, it is a great challenge to balance between the privacy gained and the loss of data utility. In this paper, we address this problem. We propose a new graph topological-based metric to improve utility preservation in social network graph anonymization. We compare the proposed approach with the amount-of-edge-change metric that popularly used in most of previous works. Experimental evaluation shows that our approach generates anonymized social network with improved utility preservation.

关键词： Social network services Measurement Privacy Communities Data privacy Computer aided software engineering Knowledge engineering

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A GPU-based high-throughput image retrieval algorithm 5

A GPU-based high-throughput image retrieval algorithm

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5th Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Zhu, Feiwen Chen, Peng Yang, Donglei Zhang, Weihua Chen, Haibo Zang, Binyu State Key Lab. of ASIC and System Fudan University China Parallel Processing Institute Fudan University China Architecture Key Lab. Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781450312332

With the development of Internet and cloud computing, multimedia data, such as images and videos, has become one of the most common data types being processed. As the scale of multimedia data being still increasing, it is vitally important to efficiently extract useful information from such a huge amount of multimedia data. However, due to the complexity of the core algorithms, multimedia retrieval applications are not only data intensive but also computationally intensive. Therefore, it has been a major challenge to accelerate the processing speed of such applications to satisfy the real-time requirement. As Graphic Processing Unit (GPU) has entered the general-propose computing domain (GPGPU), it has become one of the most popular accelerators for the applications with real-time requirements. In this paper, we parallelize a widely-used image retrieval algorithm called SURF on GPGPU, which is the core algorithm for many video and image retrieval applications. We first analyze the parallelism within SURF to guarantee that there are sufficient tasks being mapped to the large-scale computation resources in GPGPU. We then exploit some inherent GPGPU characteristics, such as 2D memory, to further boost the performance. Finally, we provide some optimization to the cooperation between CPU and GPGPU, which is generally ignored in previous designs. Experimental results show that our parallelization and optimization achieve a throughput of 340.5 frames/s on a NVIDIA GTX295 GPGPU, which is 15X faster than the maximal optimized CPU version. Compared to CUDA SURF, a state-of-the-art parallelization of SURF on GPGPU, our system achieves a speedup by a factor of 2.3X. © 2012 ACM.

关键词： Graphics processing unit

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Mixed precision training of convolutional neural networks using integer operations

arXiv

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arXiv 2018年

作者： Das, Dipankar Mellempudi, Naveen Mudigere, Dheevatsa Kalamkar, Dhiraj Avancha, Sasikanth Banerjee, Kunal Sridharan, Srinivas Vaidyanathan, Karthik Kaul, Bharat Georganas, Evangelos Heinecke, Alexander Dubey, Pradeep Corbal, Jesus Shustrov, Nikita Dubtsov, Roma Fomenko, Evarist Pirogov, Vadim Parallel Computing Lab Intel Labs India Parallel Computing Lab Intel Labs Seychelles Product Architecture Group Intel OR Singapore Software Services Group Intel OR Singapore

The state-of-the-art (SOTA) for mixed precision training is dominated by variants of low precision floating point operations, and in particular FP16 accumulating into FP32 Micikevicius et al. (2017). On the other hand, while a lot of research has also happened in the domain of low and mixed-precision Integer training, these works either present results for non-SOTA networks (for instance only AlexNet for ImageNet-1K), or relatively small datasets (like CIFAR-10). In this work, we train state-of-the-art visual understanding neural networks on ImageNet-1K dataset, with Integer operations on General Purpose (GP) hardware. In particular, we focus on Integer Fused-Multiply-and-Accumulate (FMA) operations which take two pairs of INT16 operands and accumulate results into an INT32 *** propose a shared exponent representation of tensors, and develop a Dynamic Fixed Point (DFP) scheme suitable for common neural network operations. The nuances of developing an efficient integer convolution kernel is examined, including methods to handle overflow of the INT32 accumulator. We implement CNN training for ResNet-50, GoogLeNet-v1, VGG-16 and AlexNet;and these networks achieve or exceed SOTA accuracy within the same number of iterations as their FP32 counterparts without any change in hyper-parameters and with a 1.8X improvement in end-to-end training throughput. To the best of our knowledge these results represent the first INT16 training results on GP hardware for ImageNet-1K dataset using SOTA CNNs and achieve highest reported accuracy using half precision representation. Copyright © 2018, The Authors. All rights reserved.

关键词： Convolution

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parallel pdb data retriever "pdb diving booster"

Parallel pdb data retriever "pdb diving booster"

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International Symposium on High Performance computing, ISHPC 1997

作者： Onizuka, Kentaro Noguchi, Tamotsu Saito, Minoru Akiyama, Yutaka Parallel Application TRC Lab Real World Computing Partnership Tsukuba Mitsui Building 17F 1-6-1 Takezono Tsukuba-shi Ibaraki 305 Japan

ISBN: (纸本)3540637664

A powerful PDB-data-retrieval system PDB Diving Booster, which is a collection of functions/methods for data-retrieval and datatransmission, will enhances high-performance parallel-distributed programming in the field of structural biology. This system provides with 1) functions for reading whatever irregular data in PDB file, 2) methods to access and calculate elementary data in the structured object representing a protein structure, and 3) powerful data-transmission functions/ methods for a parallel distributed environment. High performance parallel analysis of protein structures is realized only by writing a simple and short program in C++ and linking over libraries. © Springer-Verlag Berlin Heidelberg 1997.

关键词： Nonbibliographic retrieval systems

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Emerging applications for multi/many-core processors

Emerging applications for multi/many-core processors

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Victor W. Lee Yen-Kuang Chen J. Chhugani C. Kim D. Kim C.J. Hughes N. Rajagopalan Satish M. Smelyanskiy P. Dubey Parallel Computing Lab Intel Labs Intel Corporation Santa Clara California USA Parallel Computing Lab Intel Labs Intel Corporation Santa Clara California USA

There has always been a strong relationship between computer applications and computer architectures. Advances in computer architecture enable new usage models; new usage models challenge new architectures. For many decades, the interplays between applications and architectures have resulted in significant progress in the computer technologies. Recently, the computer industry adopts the multi/many-core architecture for better performance, energy efficiency and reliability. This industry-wide movement towards multi/many-core architectures opens up many opportunities for developing new classes of applications. This paper uses a few emerging applications as examples to illustrate the interplay between applications and architecture. It further discusses the key characteristics of emerging applications and how multi/many-core architecture addresses the needs of the new applications. The paper closes with recommendations for new application developers to allow better utilization of new multi/many-core processors.

关键词： Computer architecture Synchronization Data models Computers parallel processing Bandwidth Program processors

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Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Te...

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IEEE Symposium on High-Performance Computer Architecture

作者： Nitish Srivastava Hanchen Jin Shaden Smith Hongbo Rong David Albonesi Zhiru Zhang Cornell University Microsoft AI & Research Intel Parallel Computing Lab

ISBN: (数字)9781728161495

ISBN: (纸本)9781728161501

Tensor factorizations are powerful tools in many machine learning and data analytics applications. Tensors are often sparse, which makes sparse tensor factorizations memory bound. In this work, we propose a hardware accelerator that can accelerate both dense and sparse tensor factorizations. We co-design the hardware and a sparse storage format, which allows accessing the sparse data in vectorized and streaming fashion and maximizes the utilization of the memory bandwidth. We extract a common computation pattern that is found in numerous matrix and tensor operations and implement it in the hardware. By designing the hardware based on this common compute pattern, we can not only accelerate tensor factorizations but also mixed sparse-dense matrix operations. We show significant speedup and energy benefit over the state-of-the-art CPU and GPU implementations of tensor factorizations and over CPU, GPU and accelerators for matrix operations.

关键词： Tensile stress Sparse matrices Hardware Kernel Acceleration Matrix decomposition Bandwidth

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