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检索条件"机构=Lab. for Computer Architecture"
125 条 记 录,以下是1-10 订阅
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POSTER: STAR (Space-Time Adaptive and Reductive) Algorithms for Real-World Space-Time Optimality
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ACM SIGPLAN Notices 2017年 第8期52卷 455-456页
作者: Tang, Yuan You, Ronghui School of Computer Science School of Software Fudan University Shanghai Key Lab. of Intelligent Information Processing State Key Lab. of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China
It's important to hit a space-time balance for a real-world algorithm to achieve high performance on modern shared-memory multi-core or many-core systems. However, a large class of dynamic programs with more than ... 详细信息
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McRT-STM: A high performance software transactional memory system for a multi-core runtime
McRT-STM: A high performance software transactional memory s...
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2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP'06
作者: Saha, Bratin Adl-Tabatabai, Ali-Reza Hudson, Richard L. Chi, Cao Minh Hertzberg, Benjamin Programming System Lab. Microprocessor Technology Lab. Intel Corporation Computer Architecture Lab. Stanford University Palo Alto CA
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex bas... 详细信息
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Aizu supercomputer: A massively parallel system for virtual reality problems  1
Aizu supercomputer: A massively parallel system for virtual ...
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1st Aizu International Symposium on Parallel Algorithms/architecture Synthesis, AISPAS 1995
作者: Ikedo, Tsuneo Computer Architecture Lab. Department of Computer Hardware University of Aizu Aizuwakamatsu-City Fukushima Japan
The Aizu supercomputer is a massively parallel system suited to the solution of virtual reality problems and the support of multimedia applications. It employs a highly parallel MIMD architecture using a conflict-free... 详细信息
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Reliability-aware data placement for partial memory protection in embedded processors  06
Reliability-aware data placement for partial memory protecti...
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2006 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, MSPC 2006
作者: Mehrara, Mojtaba Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109
Low cost protection of embedded systems against soft errors has recently become a major concern. This issue is even more critical in memory elements that are inherently more prone to transient faults. In this paper, w... 详细信息
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Architectural optimizations for low-power, real-time speech recognition
Architectural optimizations for low-power, real-time speech ...
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CASES 2003: International Conference on Compilers, architecture, and Synthesis for Embedded Systems
作者: Krishna, Rajeev Mahlke, Scott Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor United States
The proliferation of computing technology to low power domains such as hand-held devices has lead to increased interest in portable interface technologies, with particular interest in speech recognition. The computati... 详细信息
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Ultra low-cost defect protection for microprocessor pipelines
Ultra low-cost defect protection for microprocessor pipeline...
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作者: Shyam, Smitha Constantinides, Kypros Phadke, Sujay Bertacco, Valeria Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as trans... 详细信息
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Prevention flow-control for low latency torus networks-on-chip  11
Prevention flow-control for low latency torus networks-on-ch...
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Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
作者: Joshi, Arpit Mutyam, Madhu Computer Architecture and Systems Lab. Department of Computer Science and Engineering Indian Institute of Technology Madras India
The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and keep the simplicity of a mesh network, torus network is proposed. As torus networks have... 详细信息
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STACCATO: Disjoint support decompositions from BDDs through symbolic kernels
STACCATO: Disjoint support decompositions from BDDs through ...
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2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
作者: Plaza, Stephen Bertacco, Valeria Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI United States
A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component functions have no common inputs. The decompositi... 详细信息
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How to fake 1000 registers  38
How to fake 1000 registers
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MICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture
作者: Oehmke, David W. Binkert, Nathan L. Mudge, Trevor Reinhardt, Steven K. Advanced Computer Architecture Lab. University of Michigan Ann Arbor Cray Inc.
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading). Support for both of these together r... 详细信息
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Application specific architectures: A recipe for fast, flexible and power efficient designs  2
Application specific architectures: A recipe for fast, flexi...
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2nd International Conference on Compilers, architecture, and Synthesis for Embedded Systems, CASES 2001
作者: Weaver, Chris Krishna, Rajeev Wu, Lisa Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann ArborMI United States
The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent evidence suggests that these efforts m... 详细信息
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