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POSTER: STAR (Space-Time Adaptive and Reductive) Algorithms for Real-World Space-Time Optimality

ACM SIGPLAN Notices 2017年第8期52卷 455-456页

作者： Tang, Yuan You, Ronghui School of Computer Science School of Software Fudan University Shanghai Key Lab. of Intelligent Information Processing State Key Lab. of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

It's important to hit a space-time balance for a real-world algorithm to achieve high performance on modern shared-memory multi-core or many-core systems. However, a large class of dynamic programs with more than $O(1)$ dependency achieve optimality either in space or time, but not both. In the literature, the problem is known as the fundamental space-time tradeoff. By exploiting properly on the runtime system, we show that our STAR (Space-Time Adaptive and Reductive) technique can help these dynamic programs to achieve sublinear parallel time bounds while still maintaining work-, space-, and cache-optimality in a processor- and cache-oblivious fashion. © 2017 ACM.

关键词： Real time systems

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McRT-STM: A high performance software transactional memory system for a multi-core runtime

McRT-STM: A high performance software transactional memory s...

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2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP'06

作者： Saha, Bratin Adl-Tabatabai, Ali-Reza Hudson, Richard L. Chi, Cao Minh Hertzberg, Benjamin Programming System Lab. Microprocessor Technology Lab. Intel Corporation Computer Architecture Lab. Stanford University Palo Alto CA

ISBN: (纸本)1595931899

Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming. We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The McRT-STM exports interfaces that can be used from C/C++ programs directly or as a target for compilers translating higher level linguistic constructs. We present a detailed performance analysis of various STM design tradeoffs such as pessimistic versus optimistic concurrency, undo logging versus write buffering, and cache line based versus object based conflict detection. We also show a MCAS implementation that works on arbitrary values, coexists with the STM, and can be used as a more efficient form of transactional memory. To provide a baseline we compare the performance of the STM with that of fine-grained and coarse-grained locking using a number of concurrent data structures on a 16-processor SMP system. We also show our STM performance on a non-synthetic workload - the Linux sendmail application. Copyright © 2006 ACM.

关键词： Data storage equipment

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Aizu supercomputer: A massively parallel system for virtual reality problems 1

Aizu supercomputer: A massively parallel system for virtual ...

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1st Aizu International Symposium on Parallel Algorithms/architecture Synthesis, AISPAS 1995

作者： Ikedo, Tsuneo Computer Architecture Lab. Department of Computer Hardware University of Aizu Aizuwakamatsu-City Fukushima Japan

ISBN: (纸本)081867038X

The Aizu supercomputer is a massively parallel system suited to the solution of virtual reality problems and the support of multimedia applications. It employs a highly parallel MIMD architecture using a conflict-free internetwork system. The scalab.e communication system consists of two networks: a pyramid network and a reconfigurable network using optical links. The Aizu Supercomputer has a cluster configuration and a shared memory. Each PE includes 113 SPECmark and one cluster is organized with 8 PEs. In the trial production, the supercomputer will include 1365 PEs with more than 100 GFlops at peak performance. © 1995 IEEE.

关键词： Supercomputers

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Reliability-aware data placement for partial memory protection in embedded processors 06

Reliability-aware data placement for partial memory protecti...

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2006 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, MSPC 2006

作者： Mehrara, Mojtaba Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595935789

Low cost protection of embedded systems against soft errors has recently become a major concern. This issue is even more critical in memory elements that are inherently more prone to transient faults. In this paper, we propose a reliability aware data placement technique in order to partially protect embedded memory systems. We show that by adopting this method instead of traditional placement schemes with complete memory protection, an acceptable level of fault tolerance can be achieved while incurring less area and power overhead. In this approach, each variable in the program is placed in either protected or non-protected memory area according to the profile-driven liveness analysis of all memory variables. In order to measure the level of fault coverage, we inject faults into the memory during the course of program execution in a Monte Carlo simulation framework. Subsequently, we calculate the coverage of partial protection scheme based on the number of protected, failed and crashed runs during the fault injection experiment. Copyright 2006 ACM.

关键词： Program processors

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Architectural optimizations for low-power, real-time speech recognition

Architectural optimizations for low-power, real-time speech ...

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CASES 2003: International Conference on Compilers, architecture, and Synthesis for Embedded Systems

作者： Krishna, Rajeev Mahlke, Scott Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor United States

ISBN: (纸本)1581136765

The proliferation of computing technology to low power domains such as hand-held devices has lead to increased interest in portable interface technologies, with particular interest in speech recognition. The computational demands of robust, large vocabulary speech recognition systems, however, are currently prohibitive for such low power devices. This work begins an exploration of domain specific characteristics of speech recognition that might be exploited to achieve the requisite performance within the power constraints of such devices. We focus primarily on architectural techniques to exploit the massive amounts of potential thread level parallelism apparent in this application domain, and consider the performance / power trade-offs of such architectures. Our results show that a simple, multi-threaded, multi-pipelined processor architecture can significantly improve the performance of the time-consuming search phase of modern speech recognition algorithms, and may reduce overall energy consumption by drastically reducing dissipation of static power. We also show that the primary hurdle to achieving these performance benefits is the data request rate into the memory system, and consider some initial solutions to this problem. Copyright 2003 ACM.

关键词： Speech recognition

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Ultra low-cost defect protection for microprocessor pipelines

Ultra low-cost defect protection for microprocessor pipeline...

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作者： Shyam, Smitha Constantinides, Kypros Phadke, Sujay Bertacco, Valeria Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595934510

The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown). Copyright © 2006 ACM.

关键词： Microprocessor chips

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Prevention flow-control for low latency torus networks-on-chip 11

Prevention flow-control for low latency torus networks-on-ch...

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Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

作者： Joshi, Arpit Mutyam, Madhu Computer Architecture and Systems Lab. Department of Computer Science and Engineering Indian Institute of Technology Madras India

ISBN: (纸本)9781450307208

The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and keep the simplicity of a mesh network, torus network is proposed. As torus networks have inherent circular dependency, additional effort is needed to prevent deadlock, even if deadlock free routing algorithms are used. We describe a novel flow-control mechanism to address cost/performance constraints in torus networks and ensure freedom from deadlock. Flow-control is achieved using a prevention mechanism which uses virtual cut-through switching, and deadlock freedom is achieved by considering only a single packet buffer per input port. We can simplify the router design by having a simple switch allocator, which prioritizes in-flight packets, and a single packet buffer per input port, which eliminates the need for virtual channels. Experimental validation reveals that our design achieves significant improvement in throughput, as compared to the traditional design, using significantly fewer buffers. © 2011 ACM.

关键词： Flow control

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STACCATO: Disjoint support decompositions from BDDs through symbolic kernels

STACCATO: Disjoint support decompositions from BDDs through ...

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2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

作者： Plaza, Stephen Bertacco, Valeria Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI United States

ISBN: (纸本)0780387368

A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component functions have no common inputs. The decomposition of a function is desirable for several reasons. First, it's a method to obtain a multiple-levei implementation of a function. It leads to a partition in simpler blocks that easily results in smaller areas and fewer interconnects. Moreover, it exposes a parallelism in the computation of the function that can be exploited by hardware as well as during simulation. In this paper we present a novel algorithm, STACCATO, that generates a DSD decomposition stai-ting from the BDD of a function. STACCATO is novel because 1) it provides a complete description of each decomposition, that is, it computes the "kernel" function K relating the elements of each decomposition, and 2) it has better performance than previously known algorithms. Experimental results run on both IWLS and industrial test-benches show that STACCATO'S performance is in most cases three times as fast or more than previously known solutions. © 2005 IEEE.

关键词： Boolean functions

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How to fake 1000 registers 38

How to fake 1000 registers

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MICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Oehmke, David W. Binkert, Nathan L. Mudge, Trevor Reinhardt, Steven K. Advanced Computer Architecture Lab. University of Michigan Ann Arbor Cray Inc.

ISBN: (纸本)0769524400

Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading). Support for both of these together requires a multiplicative number of registers that quickly becomes prohibitive. We overcome this limitation with the virtual context architecture (VGA), a new register-file architecture that virtualizes logical register contexts. VCA works by treating the physical registers as a cache of a much larger memory-mapped logical register space. Complete contexts, whether activation records or threads, are no longer required to reside in their entirety in the physical register file. A VCA implementation of register windows on a single-threaded machine reduces data cache accesses by 20%, providing the same performance as a conventional machine while requiring one fewer cache port. Using VCA to support multithreading enables a four-thread machine to use half as many physical registers without a significant performance loss. VCA naturally extends to support both multithreading and register windows, providing higher performance with significantly fewer registers than a conventional machine. © 2005 IEEE.

关键词： computer architecture

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Application specific architectures: A recipe for fast, flexible and power efficient designs 2

Application specific architectures: A recipe for fast, flexi...

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2nd International Conference on Compilers, architecture, and Synthesis for Embedded Systems, CASES 2001

作者： Weaver, Chris Krishna, Rajeev Wu, Lisa Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann ArborMI United States

ISBN: (纸本)1581133995

The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent evidence suggests that these efforts may be faltering as pipelining and ILP processing techniques experience diminishing returns. Application specific architectures hold great potential as an alternative means to continue scaling application performance. The approach works by specializing a design to a small domain of important applications, and it benefits from improved performance, greater power efficiency, and reduced area costs. This technique is well matched to embedded targets, where application domains are typically narrow. In this paper we present a case study of an application specific processor design. Our design, called the CryptoManiac processor, is an architecture specialized to efficiently execute cryptographic ciphers. We carefully highlight the domain specific application characteristics we identified and their accompanying optimizations in the CryptoManiac design. Detailed analyses of the design makes a strong case for application specific optimization. The CryptoManiac processor runs popular ciphers at twice the speed of a high-end general purpose processor, and the design renders nearly two orders-ofmagnitude reduction in power consumption and area costs. Finally, we identify two key challenges that stand as barriers to wide spread adoption of application specific architectures. Copyright 2001 ACM.

关键词： Cost reduction

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