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A Markov chain sequence generator for power macromodeling 02

A Markov chain sequence generator for power macromodeling

引用

IEEE/ACM International Conference on computer Aided Design (ICCAD)

作者： Liu, Xun Papaefthymiou, Marios C. Advanced Computer Architecture Lab. Dept. of Electrical Engineering University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9780780376076

In this paper, we present a novel sequence generator based on a Markov chain model. Specifically, we formulate the problem of generating a sequence of vectors with given average input probability p, average transition density d, and spatial correlation s as a transition matrix computation problem, in which the matrix elements are subject to constraints derived from the specified statistics. We also give a practical heuristic that computes such a matrix and generates a sequence of l n-bit vectors in O(nl+n2) time. Derived from a strongly mixing Markov chain, our generator yields binary vector sequences with accurate statistics, high uniformly, and high randomness. Experimental results show that our sequence generator can cover more than 99% of the parameter space. Sequences of 2,000 48-bit vectors are generated in less than 0.05 seconds, with average deviations of the signal statistics p, d, and s equal to 1.6%, 1.8%, and 2.8%, respectively. Our generator enables the detailed study of power macromodeling. Using our tool and the ISCAS-85 benchmark circuits, we have assessed the sensitivity of power dissipation to the three input statistics p, d, and s. Our investigation reveals that power is most sensitive to transition density, while only occasionally exhibiting high sensitivity to signal probability and spatial correlation. Our experiments also show that input signal imbalance can cause estimation errors as high as 100% in extreme cases, although errors are usually within 25%.

关键词： Markov processes

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An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

An adaptive, non-uniform cache structure for wire-delay domi...

引用

Tenth International Conference on Architectural Support for Programming Languages and Operating Systems

作者： Kim, Changkyu Burger, Doug Keckler, Stephen W. Comp. Architecture and Technol. Lab. Department of Computer Sciences The University of Texas at Austin Austin TX United States

ISBN: (纸本)9781581135749

Growing wire delays will force substantive changes in the designs of large caches. Traditional cache architectures assume that each level in the cache hierarchy has a single, uniform access time. Increases in on-chip communication delays will make the hit time of large on-chip caches a function of a line's physical location within the cache. Consequently, cache access times will become a continuum of latencies rather than a single discrete latency. This non-uniformly can be exploited to provide faster access to cache lines in the portions of the cache that reside closer to the processor. In this paper, we evaluate a series of cache designs that provides fast hits to multi-megabyte cache memories. We first propose physical designs for these Non-Uniform Cache architectures (NUCAs). We extend these physical designs with logical policies that allow important data to migrate toward the processor within the same level of the cache. We show that, for multi-megabyte level-two caches, an adaptive, dynamic NUCA design achieves 1.5 times the IPC of a Uniform Cache architecture of any size, outperforms the best static NUCA scheme by 11%, outperforms the best three-level hierarchy-while using less silicon area-by 13%, and comes within 13% of an ideal, minimal hit latency solution.

关键词： computer architecture

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The energy efficiency of CMP vs. SMT for multimedia workloads 04

The energy efficiency of CMP vs. SMT for multimedia workload...

引用

2004 International Conference on Supercomputing

作者： Sasanka, Ruchira Adve, Sarita V. Chen, Yen-Kuang Debes, Eric Department of Computer Science University of Illinois Urbana-Champaign United States Architecture Research Lab. Intel Corporation United States

ISBN: (纸本)9781581138399

This paper compares the energy efficiency of chip multiprocessing (CMP) and simultaneous multithreading (SMT) on modern out-of-order processors for the increasingly important multimedia applications. Since performance is an important metric for real-time multimedia applications, we compare configurations at equal performance. We perform this comparison for a large number of performance points derived using different processor architectures and frequencies/voltages. We find that for the design space explored, for each workload, at each performance point, CMP is more energy efficient than SMT. The difference is small for two thread systems, but large (18% to 44%) for four thread systems. We also find that the best SMT and the best CMP configuration for a given performance target have different architecture and frequency/voltage. Therefore, their relative energy efficiency depends on a subtle interplay between various factors such as capacitance, voltage, IPC, frequency, and the level of clock gating, as well as workload features. We perform a detailed analysis considering these factors and develop a mathematical model to explain these results. Although CMP shows a clear energy advantage for four-thread (and higher) workloads, it comes at the cost of increased silicon area. We therefore investigate a hybrid solution where a CMP is built out of SMT cores, and find it to be an effective compromise. Finally, we find that we can reduce energy further for CMP with a straightforward application of previously proposed techniques of adaptive architectures and dynamic voltage/frequency scaling. CMP, SMT, Energy Efficiency, Multimedia.

关键词： Multimedia systems

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Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture 03

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS arc...

引用

30th Annual International Symposium on computer architecture

作者： Sankaralingam, Karthikeyan Nagarajan, Ramadass Liu, Haiming Kim, Changkyu Huh, Jaehyuk Burger, Doug Keckler, Stephen W. Moore, Charles R. Comp. Architecture and Technol. Lab. Department of Computer Sciences The University of Texas at Austin Austin TX United States

ISBN: (纸本)9780769519456

This paper describes the polymorphous TRIPS architecture which can be configured for different granularities and types of parallelism. TRIPS contains mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism. To adapt to small and large-grain concurrently, the TRIPS architecture contains four out-of-order, 16-wide-issue Grid Processor cores, which can be partitioned when easily extractable fine-grained parallelism exists. This approach to polymorphism provides better performance across a wide range of application types than an approach in which many small processors are aggregated to run workloads with irregular parallelism. Our results show that high performance can be obtained in each of the three modes-ILP, TLP, and DLP-demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.

关键词： computer architecture

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An adaptive low-power transmission scheme for on-chip networks

An adaptive low-power transmission scheme for on-chip networ...

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15th International Symposium on System Synthesis

作者： Worm, Frédéric Thiran, Patrick Ienne, Paolo De Micheli, Giovanni Processor Architecture Laboratory EPFL Lausanne Switzerland Lab. for Computer Communications EPFL Lausanne Switzerland Computer Systems Laboratory Stanford University Stanford CA United States

Systems-on-Chip (SoC) are evolving toward complex heterogeneous multiprocessors made of many predesigned macrocells or subsystems with application-specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme;it minimises the interconnect voltage swing and frequency subject to workload requirements and S/N conditions. Simulation results show that tangible savings in energy can be attained while achieving at the same time more robustness to large variations in actual workload, noise, and technology quality (all quantities easily mispredicted in very complex systems and advanced technologies). It can be argued that traditional worst-case correct-by-design paradigm will be less and less applicable in future multibillion transistor SoC and deep sub-micron technologies;this work represents a first example towards robust adaptive designs.

关键词： Microprocessor chips

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Evolutionary computing: AISB international workshop manchester, UK, april 7-8, 1997 selected papers

引用

AISB International Workshop on Evolutionary Computing, 1997

作者： Corne, David Shapiro, Jonathan L. University of Reading Department of Computer Science Parallel Emergent and Distributed Architecture Lab. Reading United Kingdom University of Manchester Department of Computer Science Manchester United Kingdom

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Architectural issues in Java runtime systems

Architectural issues in Java runtime systems

引用

Sixth International Symposium on High-Performance computer architecture

作者： Radhakrishnan, R. Vijaykrishnan, N. John, L.K. Sivasubramaniam, A. Lab. for Computer Architecture Dept. of Electrical and Comp. Eng. The University of Texas at Austin Austin TX United States

The Java Virtual Machine (JVM) is the corner stone of Java technology, and its efficiency in executing the portable Java bytecodes is crucial for the success of this technology. Interpretation, Just-In-Time (JIT) compilation, and hardware realization are well known solutions for a JVM, and previous research has proposed optimizations for each of these techniques. However, each technique has its pros and cons and may not be uniformly attractive for all hardware platforms. Instead, an understanding of the architectural implications of JVM implementations with real applications, can be crucial to the development of enabling technologies for efficient Java runtime system development on a wide range of platforms (from resource-rich servers to resource-constrained hand-held/embedded systems). Towards this goal, this paper examines architectural issues, from both the hardware and JVM implementation perspectives. It specifically explores the potential of a smart JIT compiler strategy that can dynamically interpret or compile based on associated costs, investigates the CPU and cache architectural support that would benefit JVM implementations, and examines the synchronization support for enhancing performance, using applications from the SpecJVM98 benchmarks.

关键词： Supervisory and executive programs

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Integrating superscalar processor components to implement register caching 01

Integrating superscalar processor components to implement re...

引用

2001 International Conference on Supercomputing

作者： Postiff, M. Greene, D. Raasch, S. Mudge, T. Advanced Computer Architecture Lab. University of Michigan 1301 Beal Ave. Ann Arbor MI 48109-2122 United States

ISBN: (纸本)9781581134100

A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical register file can be slow, particularly in the context of a wide-issue processor which requires an even larger physical register file, and many read and write ports. Previous work has suggested that a register cache can be used to address this problem. This paper proposes a new register caching mechanism in which a number of good features from previous approaches am combined with existing out-of-order processor hardware to implement a register cache for a large logical register file. It does so by separating the logical register file from the physical register file and using a modified form of register renaming to make the cache easy to implement. The physical register file in this configuration contains fewer entries than the logical register file and is designed so that the physical register file acts as a cache f or the logical register file, which is the backing store. The tag information in this caching technique is kept in the register alias table and the physical register file. It is found that the caching mechanism improves IPC up to 20% over an un-cached large logical register file and has performance near to that of a logical register file that is both large and fast.

关键词： Shift registers

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Restructuring field layouts for embedded memory systems 06

Restructuring field layouts for embedded memory systems

引用

Design, Automation and Test in Europe, DATE'06

作者： Keoncheol, Shin Jungeun, Kim Seonggun, Kim Hwansoo, Han Division of Computer Science KAIST Daejeon Korea Republic of System Architecture Lab. Samsung Electronics Corp. Suwon Korea Republic of

ISBN: (纸本)3981080114

In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remapping scheme for dynamically allocated structures in order to provide better locality than conventional field layouts. Our proposed scheme reduces cache miss rates drastically by aggregating and grouping fields from multiple instances of the same structure, which implies the performance improvement and power reduction. Our methodology will become more important in the design space exploration, especially as the embedded systems for data oriented application become prevalent. Experimental results show that average LI and L2 data cache misses are reduced by 23% and 17%, respectively. Due to the enhanced localities, our remapping achieves 13% faster execution time on average than original programs. It also reduces power consumption by 18% for data cache.

关键词： Storage allocation (computer)

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A virtual-physical on-chip cache for shared memory multiprocessors

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3rd International Conference on Parallel Processing, Euro-Par 1997

作者： Kim, Dongwook Lee, Joonwon Computer Architecture Lab. Computer Science Department Korea Advanced Institute of Science and Technology 373-1 Kusung-dong Yusung-ku Taejon 305-701 Korea Republic of

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