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23rd International Conference on Information Processing in Medical Imaging, IPMI 2013

作者： Ge, Bao Guo, Lei Zhu, Dajiang Zhang, Tuo Hu, Xintao Han, Junwei Liu, Tianming College of Physics and Information Technology Shaanxi Normal University Xi'an China School of Automation Northwestern Polytechnical University Xi'an China Cortical Architecture Imaging and Discovery Lab. Department of Computer Science University of Georgia Athens GA United States

ISBN: (纸本)9783642388675

Modeling the human brain as a network has been widely considered as a powerful approach to investigating the brain's structural and functional systems. However, many previous approaches focused on a single scale of brain network and the multi-scale nature of brain networks has been rarely explored yet. This paper put forward a novel framework to construct multi-scale common networks of brains via multi-scale spectral clustering of fiber connections among DICCCOLs. Specifically, the recently developed and publicly released DICCCOLs provide the nodal structural and functional correspondence across individuals, and thus the employed multi-scale spectral clustering algorithm divided the DICCCOL landmarks and their connections into sub-networks with correspondences on multiple scales. Experimental results showed the promise of the constructed multi-scale networks in applications of structural and functional connectivity mapping. As an application example, these multi-scale networks are used to guide the identification of multi-scale common fiber bundles across individuals and to facilitate the bundle's functional role analysis, which could enable other tract-based and network-based analyses in the future. © 2013 Springer-Verlag.

关键词： Clustering algorithms

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Evaluating dynamics and bottlenecks of memory collab.ration in cluster systems 12

Evaluating dynamics and bottlenecks of memory collaboration ...

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12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, CCGrid 2012

作者： Samih, Ahmad Wang, Ren Maciocco, Christian Tai, Tsung-Yuan Charlie Duan, Ronghui Duan, Jiangang Yan, Solihin Dept. of Electical and Computer Engineering North Carolina State University Raleigh NC United States System Architecture Lab. Intel Labs. Hillsboro OR United States Software and Services Group Intel Corp. Shanghai China

ISBN: (纸本)9780769546919

With the fast development of highly-integrated distributed systems (cluster systems), designers face interesting memory hierarchy design choices while attempting to avoid the notorious disk swapping. Swapping to the free remote memory through Memory Collab.ration has demonstrated its cost-effectiveness compared to over provisioning the cluster for peak load requirements. Recent memory collab.ration studies propose several ways on accessing the under-utilized remote memory in static system configurations, without detailed exploration of the dynamic memory collab.ration. Dynamic collab.ration is an important aspect given the run-time memory usage fluctuations in clustered systems. Further, as the interest in memory collab.ration grows, it is crucial to understand the existing performance bottlenecks, overheads, and potential optimization. In this paper we address these two issues. First, we propose an Autonomous Collab.rative Memory System (ACMS) that manages memory resources dynamically at run time to optimize performance. We implement a prototype realizing the proposed ACMS, experiment with a wide range of real-world applications, and show up to 3x performance speedup compared to a non-collab.rative memory system without perceivable performance impact on nodes that provide memory. Second, we analyze, in depth, the end-to-end memory collab.ration overhead and pinpoint the corresponding bottlenecks. © 2012 IEEE.

关键词： Cost effectiveness

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Using semantic differential scales to assess the subjective perception of auditory warning signals 21

Using semantic differential scales to assess the subjective ...

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21st International Conference on Digital Audio Effects, DAFx 2018

作者： Vieira, Joana Santos, Jorge Almeida Noriega, Paulo ALGORITMI University of Minho Braga CCG - Centre for Computer Graphics Guimarães Portugal School of Psychology University of Minho Braga Portugal Ergonomics Lab. Faculty of Human Kinetics CIAUD Lisbon School of Architecture Universidade de Lisboa Portugal

The relationship between physical acoustic parameters and the subjective responses they evoke is important to assess in audio alarm design. While the perception of urgency has been thoroughly investigated, the perception of other variables such as pleasantness, negativeness and irritability has not. To characterize the psychological correlates of variables such as frequency, speed, rhythm and onset, twenty-six participants evaluated fifty-four audio warning signals according to six different semantic differential scales. Regression analysis showed that speed predicted mostly the perception of urgency, preoccupation and negativity;frequency predicted the perception of pleasantness and irritability;and rhythm affected the perception of urgency. No correlation was found with onset and offset times. These findings are important to human-centred design recommendations for auditory warning signals. Copyright © 2018 *** rights reserved.

关键词： Regression analysis

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Cooperative cache system: A low power cache system for embedded processors

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IEICE TRANSACTIONS ON ELECTRONICS 2007年第4期E90C卷 708-717页

作者： Park, Gi-Ho Lee, Kil-Whan Han, Tack-Don Kim, Shin-Dug Processor Architecture Lab. Samsung Electronics South Korea AP Team Samsung Electronics South Korea Department of Computer Science Yonsei University Seoul South Korea

This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 μm 4-metal process technology. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.

关键词： low power cache cooperative cache block size associativity embedded processor

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Using coherence information and decay techniques to optimize L2 cache leakage in CMPs

Using coherence information and decay techniques to optimize...

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38th International Conference on Parallel Processing, ICPP-2009

作者： Monchiero, Matteo Canal, Ramon González, Antonio Exascale Computing Lab. Palo Alto CA 94034 United States Dept. of Computer Architecture Universitat Politécnica de Catalunya Barcelona 08034 Spain Intel Barcelona Research Center Intel Labs- UPC Barcelona 08034 Spain

ISBN: (纸本)9780769538020

This paper evaluates several techniques to save leakage in CMP L2 caches by selectively switching off the less used lines. We primarily focus on private snoopy L2 caches. In this case, coherence must be enforced in all situations and specially when a line is turned off to save power. In particular, we introduce three techniques: the first one turns off the cache lines by using the coherence protocol invalidations, the second one is an implementation of a cache decay technique specific for coherent caches, the third one is a performance-optimized decay-based technique for coherent caches. Experimental results, carried out by using accurate performance/thermal/energy models, show that appreciable power savings can be achieved by properly designing a leakage optimization technique. We target a CMP composed of 4 cores and 1 to 8 MB of total cache. For 4MB, the proposed techniques show a 13%, 30%, and 21% energy reduction, respectively, at the cost of 0%, 8%, and 2% performance loss. For other cache sizes the behavior is qualitatively similar. © 2009 IEEE.

关键词： Cache memory

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Burn your memory away: One-time use video capture and storage device to encourage memory appreciation

Burn your memory away: One-time use video capture and storag...

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27th International Conference Extended Abstracts on Human Factors in Computing Systems, CHI 2009

作者： Chi, Pei-Yu Chiu, Carnaven Xiao, Xiao Chung, Keywon MIT Media Lab. 20 Ames Street Cambridge MA 02139 United States MIT Architecture 20 Ames Street Cambridge MA 02139 United States MIT Computer Science 20 Ames Street Cambridge MA 02139 United States

ISBN: (纸本)9781605582474

Although modern ease of access to technology enables many of us to obsessively document our lives, much of the captured digital content is often disregarded and forgotten on storage devices, with no concerns of cost or decay. Can we design technology that helps people better appreciate captured memories? What would people do if they only had one more chance to relive past memories? In this paper, we present a prototype design, PY-ROM, a matchstick-like video recording and storage device that burns itself away after being used. This encourages designers to consider lifecycles and human-computer relationships by integrating physical properties into digitally augmenting everyday objects.

关键词： Ubiquitous computing

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Timing analysis using propositional satisfiability

Timing analysis using propositional satisfiability

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5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998

作者： E Silva, Luís Guerra Silva, João P. Marques Silveira, Luís Miguel Sakallah, Karem A. Cadence European Laboratories INESC Institute Superior Técnico R. Alves Redol 9 Lisboa1000 Portugal Electrical Engineering and Computer Science Dept. Advanced Computer Architecture Lab. University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0780350081

The existence of false paths represents a significant and computationally complex problem in the timing analysis of combinational and sequential circuits. In this paper we describe Propositional Satisfiability based algorithms for timing analysis, which introduce significant performance improvements over existing procedures. In particular, we address the problems of circuit delay computation and path delay validation, describing algorithms and providing experimental results for both problems. © 1998 IEEE.

关键词： Timing circuits

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A configurable network protocol for cluster based communications using modular hardware primitives on an intelligent NIC 03

A configurable network protocol for cluster based communicat...

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2003 ACM/IEEE Conference on Supercomputing, SC 2003

作者： Jaganathan, Ranjesh G. Underwood, Keith D. Sass, Ron Parallel Architecture Research Lab. Holcombe Department of Electrical and Computer Engineering Clemson University Clemson SC 29634-0915 United States Sandia National Laboratories MS-1110 P.O. Box 5800 Albuquerque NM 87185-1110 United States

ISBN: (纸本)1581136951

The high overhead of generic protocols like TCP/IP provides strong motivation for the development of a better protocol architecture for cluster-based parallel computers. Reconfigurable computing has a unique opportunity to contribute hardware level protocol acceleration while retaining the flexibility to adapt to changing needs. Specifically, applications on a cluster have various quality of service needs. In addition, these applications typically run for a long time relative to the reconfiguration time of an FPGA. Thus, it is possible to provide application-specific protocol processing to improve performance and reduce space utilization. Reducing space utilization permits the use of a greater portion of the FPGA for other application-specific processing. This paper focuses on work to create a set of parameterizable components that can be put together as needed to obtain a customized protocol for each application. To study the feasibility of such an architecture, hardware components were built that can be stitched together as needed to provide the required functionality. Feasibility is demonstrated using four different protocol configurations, namely: (1) unreliable packet transfer;(2) reliable, unordered message transfer without duplicate elimination;(3) reliable, unordered message transfer with duplicate elimination;and (4) reliable, ordered message transfer with duplicate elimination. The different configurations illustrate trade-offs between chip space and functionality. © 2003 ACM.

关键词： Field programmable gate arrays (FPGA)

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Identifying spatial structure of urban functional centers using travel survey data: A case study of Singapore

Identifying spatial structure of urban functional centers us...

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1st ACM SIGSPATIAL International Workshop on Computational Models of Place, COMP 2013

作者： Zhong, Chen Huang, Xianfeng Arisona, Stefan Müller Schmitt, Gerhard Future Cities Laboratory Department of Architecture ETH Zurich 8092 Zurich Switzerland State Key Lab. of Information Engineering in Surveying Mapping and Remote Sensing Wuhan University 430079 Wuhan China School of Computer Engineering Nanyang Technological University 639798 Singapore Singapore

ISBN: (纸本)9781450325356

Identifying the spatial structure generated by urban movements contributes to a better understanding of urban dynamics and is crucial to urban planning applications. Despite a number of studies concerning functional urban space, related research is still in a development phase, especially using emerging urban movement data. This study proposes a centrality index and attractiveness indices for detecting the urban spatial structure of functional centers and their spatial impacts using transportation data. The basic idea of these indices is to build a relationship between the activity patterns (distribution, density, and diversity) and urban form. Accordingly, measurements, spatial analysis, and clustering methods are presented. Taking Singapore as a case study area, we applied the proposed indices and measurements to travel survey data of different years, through which centers of urban activities as well as the changing urban form are detected and compared quantitatively. Our approach yields important insights into urban phenomena generated by human movements. It represents a novel way of quantitative urban analysis and explicit urban change identification. Copyright © 2013 ACM.

关键词： Urban planning

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Width minimization of two-dimensional CMOS cells using integer programming 96

Width minimization of two-dimensional CMOS cells using integ...

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Proceedings of the 1996 IEEE/ACM international conference on computer-aided design

作者： Avaneendra Gupta John P. Hayes Advanced Computer Architecture Lab. Dept. of Electrical Engr. and Computer Science The University of Michigan Ann Arbor MI and Design Technology Division Intel Corporation 2200 Mission College Blvd. Santa Clara CA Advanced Computer Architecture Lab. Dept. of Electrical Engr. and Computer Science The University of Michigan Ann Arbor MI

ISBN: (纸本)9780818675973

We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Run-times for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.

关键词： CMOS networks

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