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Workshop on Visual Performance Analysis (VPA)

作者： Lucas Theisen Aamer Shah Felix Wolf Department of Computer Science RWTH Aachen University Aachen Germany German Research School for Simulation Sciences Laboratory for Parallel Programming Aachen Germany

High-dimensional torus networks are becoming common in flagship HPC systems, with five of the top ten systems in June 2014 having networks with more than three dimensions. Although such networks combine performance with scalability at reasonable cost, the challenge of how to achieve optimal performance remains. Tools are needed to help understand how well the traffic is distributed among the many dimensions. This involves not only capturing network traffic but also its comprehensible visualization. However, visualizing such networks requires projecting multiple dimensions onto a two-dimensional screen, which is naturally challenging. To tackle this problem, in this position paper, we propose a visualization technique which can display traffic on torus networks with up to six dimensions. Our fundamental approach is to simultaneously present multiple views of the same network section, with each view visualizing different dimensions. Furthermore, we leverage the multiple-coordinate system concept and combine it with a customized polygon view to provide both a global and a zoomed-in perspective of the network. By interactively linking all the views, our technique makes it possible to analyze how the communication pattern of an application is mapped onto a network.

关键词： Data visualization Visualization Monitoring Measurement Educational institutions Joining processes Hardware

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Some essential techniques for developing efficient petascale applications

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Journal of Physics: Conference Series 2008年第1期125卷 012036 (15-012036 (15页

作者： Kalé, L.V. Parallel Programming Laboratory Computer Science Department University of Illinois at Urbana-Champaign Urbana IL 61810 United States

Multiple petaflops-lass machines will appear during the coming year, and many multipetaflops machines are on the anvil. It will be a substantial challenge to make existing parallel CSE applications run efficiently on them, and even more challenging to design new applications that can effectively leverage the large computational power of these machines. Multicore chips and SMP nodes are becoming popular and pose challenges of their own. Further, a new set of challenges in productivity arise, especially if we wish to have a broader set of applications and people to use these machines. Reviewed here is a set of techniques that have proved useful in multiple parallel applications that have scaled to tens of thousands of processors, on machines such as the Blue Gene/L, Blue Gene/P, Cray XT3, and XT4. New challenges and potential solutions for the performance issues are identified. Issues presented by multicore chips and SMP nodes also rre addressed. Also reviewed are some new and old ideas for increasing productivity in parallel programming substantially. © 2008 IOP Publishing Ltd.

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Synchronizing the timestamps of concurrent events in traces of hybrid MPI/OpenMP applications

Synchronizing the timestamps of concurrent events in traces ...

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作者： Becker, Daniel Geimer, Markus Rabenseifner, Rolf Wolf, Felix German Research School for Simulation Sciences Laboratory for Parallel Programming 52062 Aachen Germany RWTH Aachen University Department of Computer Science 52056 Aachen Germany Forschungszentrum Jülich Jülich Supercomputing Centre 52428 Jülich Germany University of Stuttgart High Performance Computing-Center 70550 Stuttgart Germany

ISBN: (纸本)9780769542201

Event traces are helpful in understanding the performance behavior of parallel applications since they allow the indepth analysis of communication and synchronization patterns. However, the absence of synchronized clocks on most cluster systems may render the analysis ineffective because inaccurate relative event timings may misrepresent the logical event order and lead to errors when quantifying the impact of certain behaviors or confuse the users of time-line visualization tools by showing messages flowing backward in time. In our earlier work, we have developed a scalable algorithm that eliminates inconsistent inter-process timings postmortem in traces of pure MPI applications. Since hybrid programming, the combination of MPI and OpenMP in a single application, is becoming more popular on clusters in response to rising numbers of cores per chip and widening shared-memory nodes, we present an extended version of the algorithm that in addition to message-passing event semantics also preserves and restores shared-memory event semantics. © 2010 IEEE.

关键词： Message passing

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A dynamic accelerator-cluster architecture

A dynamic accelerator-cluster architecture

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41st International Conference on parallel Processing Workshops, ICPPW 2012

作者： Rinke, Sebastian Becker, Daniel Lippert, Thomas Prabhakaran, Suraj Westphal, Lidia Wolf, Felix Laboratory for Parallel Programming German Research School for Simulation Sciences 52062 Aachen Germany Department of Computer Science RWTH Aachen University 52062 Aachen Germany Corporate Technology Siemens AG 81739 München Germany Jülich Supercomputing Centre 52428 Jülich Germany MAGMA Giessereitechnologie GmbH 52072 Aachen Germany

ISBN: (纸本)9780769547954

Accelerators such as graphics processing units (GPUs) provide an inexpensive way of improving the performance of cluster systems. In such an arrangement, the individual nodes of the cluster are directly connected to one or more accelerator devices via PCI Express. This results in a static mapping of accelerators onto compute nodes, where each accelerator can only be accessed from exactly one compute node. While this static mapping enables efficient data transfers between a given accelerator and the compute node it belongs to, differing computational demands across jobs may, however, produce either underutilized accelerators or nodes whose computational demands cannot be satisfied with the number of accelerators available to them. In particular, smaller numbers of GPUs available per node may enforce explicit MPI parallelism across compute nodes where it is not necessary. To address this limitation, we propose a novel accelerator-cluster architecture in which network-attached accelerators are dynamically assigned to compute nodes. This allows not only their optimal utilization but also a more precise match between application requirements and accelerator hardware. We outline the general concept of our dynamic architecture and show that it can offer substantial benefits to certain classes of applications without significantly harming the performance of others. © 2012 IEEE.

关键词： Memory architecture

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A comparative analysis of load balancing algorithms applied to aweather forecast model

A comparative analysis of load balancing algorithms applied ...

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IEEE International Symposium on Computer Architecture and High Performance Computing

作者： Rodrigues, Eduardo R. Navaux, Philippe O. A. Panetta, Jairo Fazenda, Alvaro Mendes, Celso L. Kale, Laxmikant V. Institute of Informatics Federal University of Rio Grande do Sul Porto Alegre Brazil Center for Weather Forecast and Climate Studies INPE Cachoeira Paulista Brazil Science and Technology Department Federal University of Sao Paulo Sao Jose dos Campos Brazil Parallel Programming Laboratory University of Illinois at Urbana-Champaign Urbana United States

ISBN: (纸本)9780769542164

Among the many reasons for load imbalance in weather forecasting models, the dynamic imbalance caused by localized variations on the state of the atmosphere is the hardest one to handle. As an example, active thunderstorms may substantially increase load at a certain timestep with respect to previous timesteps in an unpredictable manner - after all, tracking storms is one of the reasons for running a weather forecasting model. In this paper, we present a comparative analysis of different load balancing algorithms to deal with this kind of load imbalance. We analyze the impact of these strategies on computation and communication and the effects caused by the frequency at which the load balancer is invoked on execution time. This is done with-out any code modification, employing the concept of processor virtualization, which basically means that the domain is over-decomposed and the unit of rebalance is a sub-domain. With this approach, we were able to reduce the execution time of a full, real-world weather model. © 2010 IEEE.

关键词： Weather forecasting

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BULK-SYNCHRONOUS parallel ALGORITHMS FOR QR AND QZ MATRIX FACTORISATION

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parallel Algorithms and Applications. 1997年第1-2期11卷 97-112页

作者： RADU CALINESCU DAVID J. EVANS [a] Programming Research Group Oxford University Computing Laboratory Oxford 0X1 3QD UK [b] Parallel Algorithms Research Centre Loughborough University of Technology Loughborough Leicestershire LE11 3TU UK

This paper presents bulk-synchronous parallel (BSP) algorithms for linear system solving through QR and QZ factorisation. The two new algorithms are analysed in terms of the BSP cost model, and portable implementations of the QR and QZ decomposition methods are devised using the Oxford BSP Library. The experimental results obtained on a shared-memory multiprocessor accurately match the theoretical predictions, permitting a thorough comparison of the two algorithms.

关键词： linear system solving QR factorisation QZ factorisation bulk-synchronous parallel model

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How file access patterns influence interference among cluster applications

How file access patterns influence interference among cluste...

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IEEE International Conference on Cluster Computing

作者： Chih-Song Kuo Aamer Shah Akihiro Nomura Satoshi Matsuoka Felix Wolf Department of Computer Science RWTH Aachen University Aachen Germany German Research School for Simulation Sciences Laboratory for Parallel Programming Aachen Germany Tokyo Institute of Technology Global Scientific Information and Computing Center Tokyo Japan

On large-scale clusters, tens to hundreds of applications can simultaneously access a parallel file system, leading to contention and in its wake to degraded application performance. However, the degree of interference depends on the specific file access pattern. On the basis of synchronized time-slice profiles, we compare the interference potential of different file access patterns. We consider both micro-benchmarks, to study the effects of certain patterns in isolation, and realistic applications to gauge the severity of such interference under production conditions. In particular, we found that writing large files simultaneously with small files can slow down the latter at small chunk sizes but the former at larger chunk sizes. We further show that such effects can seriously affect the runtime of real applications-up to a factor of five in one instance. In the future, both our insights and profiling techniques can be used to automatically classify the interference potential between applications and to adjust scheduling decisions accordingly.

关键词： Interference Servers Throughput Benchmark testing Market research Degradation Aggregates

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How File-access Patterns Inuence the Degree of I/O Interference between Cluster Applications

Supercomputing Frontiers and Innovations

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Supercomputing Frontiers and Innovations 2019年第2期6卷 29-55页

作者： Shah, Aamer Kuo, Chih-Song Nomura, Akihiro Matsuoka, Satoshi Wolf, Felix Laboratory for Parallel Programming Technische Universita•t Darmstadt Darmstadt Germany Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Global Scientic Information and Computing Center Tokyo Institute of Technology Tokyo Japan Department of Mathematical and Computing Science Tokyo Institute of Technology Tokyo Japan

On large-scale clusters, tens to hundreds of applications can simultaneously access a parallel le system, leading to contention and, in its wake, to degraded application performance. In this article, we analyze the inuence of le-access patterns on the degree of interference. As it is by experience most intrusive, we focus our attention on write-write contention. We observe considerable dierences among the interference potentials of several typical write patterns. In particular, we found that if one parallel program writes large output les while another one writes small checkpointing les, then the latter is slowed down when the checkpointing les are small enough and the former is vice versa. Moreover, applications with a few processes writing large output les already can signicantly hinder applications with many processes from checkpointing small les. Such eects can seriously impact the runtime of real applications|up to a factor of ve in one instance. Our insights and measurement techniques oer an opportunity to automatically classify the interference potential between applications and to adjust scheduling decisions accordingly. © The Authors 2019. This paper is published with open access at ***

关键词： Benchmarking

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Synchronizing the Timestamps of Concurrent Events in Traces of Hybrid MPI/OpenMP Applications

Synchronizing the Timestamps of Concurrent Events in Traces ...

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IEEE International Conference on Cluster Computing

作者： Daniel Becker Markus Geimer Rolf Rabenseifner Felix Wolf Department of Computer Science RWTH Aachen University Aachen Germany German Research School for Simulation Sciences Laboratory for Parallel Programming Aachen Germany Forschungszentrum Jülich Jülich Supercomputing Centre Jülich Germany University of Stuttgart High Performance Computing-Center Stuttgart Germany

Event traces are helpful in understanding the performance behavior of parallel applications since they allow the in-depth analysis of communication and synchronization patterns. However, the absence of synchronized clocks on most cluster systems may render the analysis ineffective because inaccurate relative event timings may misrepresent the logical event order and lead to errors when quantifying the impact of certain behaviors or confuse the users of time-line visualization tools by showing messages flowing backward in time. In our earlier work, we have developed a scalable algorithm that eliminates inconsistent inter-process timings postmortem in traces of pure MPI applications. Since hybrid programming, the combination of MPI and OpenMP in a single application, is becoming more popular on clusters in response to rising numbers of cores per chip and widening shared-memory nodes, we present an extended version of the algorithm that in addition to message-passing event semantics also preserves and restores shared-memory event semantics.

关键词： Clocks Message systems Semantics Synchronization Algorithm design and analysis Interpolation

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Managing Power Demand and Load Imbalance to Save Energy on Systems with Heterogeneous CPU Speeds

Managing Power Demand and Load Imbalance to Save Energy on S...

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International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Edson Luiz Padoin Matthias Diener Philippe O. A. Navaux Jean-François Méhaut Department of Exact Sciences and Engineering (DCEEng) Regional University of Northwest of Rio Grande do Sul (UNIJUI) Ijuí Brazil Parallel Programming Laboratory (PPL) University of Illinois at Urbana-Champaign (UIUC) Urbana-Champaign USA Informatics Institute Federal University of Rio Grande do Sul (UFRGS) Porto Alegre Brazil University Grenoble Alpes Grenoble France

Different simulations of real problems have been executed in High Performance Computing systems. However, the power consumption of these systems is an increasing concern once more energy are consumed to large simulations. In this context, load balancers emerge as a promising alternative for supporting the computational science methods. In response to this challenge, we developed a new heterogeneous energy-aware load balancer called H-ENERGYLB to reduce the average power demand of systems with heterogeneous processors and save energy when scientific applications with imbalanced load are executed. Our new load balancing strategy combines dynamic load balancing with DVFS techniques to mitigate the imbalanced workloads in order to reduce the clock frequency of underloaded computing cores which experience some residual imbalance even after tasks are remapped. Experiments with three applications on two different heterogeneous architectures show that H-ENERGYLB results in power reductions of 7.14% in average with the energy saving of 36.6% in average compared to others load balancers.

关键词： Program processors Load management Task analysis Power demand Clocks Runtime Load modeling

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