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International Symposium on High Performance distributed computing

作者： A. Choudhary M. Kandemir H. Nagesh J. No X. Shen V. Taylor S. More R. Thakur Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA

With the increasing number of scientific applications manipulating huge amounts of data, effective data management is an increasingly important problem. Unfortunately, so far the solutions to this data management problem either require deep understanding of specific storage architectures and file layouts (as in high-performance file systems) or produce unsatisfactory I/O performance in exchange for ease-of-use and portability (as in relational DBMSs). In this paper we present a new environment which is built around an active meta-data management system (MDMS). The key components of our three-tiered architecture are user application, the MDMS, and a hierarchical storage system (HSS). Our environment overcomes the performance problems of pure database-oriented solutions, while maintaining their advantages in terms of ease-of-use and portability. The high levels of performance are achieved by the MDMS, with the aid of user-specified directives. Our environment supports a simple, easy-to-use yet powerful user interface, leaving the task of choosing appropriate I/O techniques to the MDMS. We discuss the importance of an active MDMS and show how the three components, namely application, the MDMS, and the HSS, fit together. We also report performance numbers from our initial implementation and illustrate that significant improvements are made possible without undue programming effort.

关键词： Large-scale systems distributed computing High performance computing Data visualization Engineering management Concurrent computing Relational databases Art Data analysis Image analysis

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Semantic configuration management model using a path dependence flow graph

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Systems and Computers in Japan 1999年第5期30卷 47-55页

作者： Naoi, Kuniaki Takahashi, Naohisa NTT Software Laboratories Musashino 180 Japan NTT Optical Netwk. Syst. Labs. Musashino 180 Japan Waseda University Global Computing Laboratory NTT Software Laboratories Technical University Berlin Germany Info. Processing Society of Japan Japan Soc. Software Sci. Technol. ACM IEEE Computer Society University of Electro-Communications Tokyo Institute of Technology NTT Elec. Commun. Laboratories Parallel Distributed Arch.'s Res. G. NTT Optical Netwk. Syst. Labs. Info. Processing Society of Japan ACM

If a program is not executed as expected, we say that a semantic error has occurred in the program. As is well known, semantic errors sometimes appear in a program because the modification intention was not correctly reflected in the new configuration. In order to avoid as many semantic errors as possible, as well as to efficiently locate errors, the authors are developing a semantic configuration management (SCM) model that is capable of efficiently performing various analyses of programs in a unified framework. Previously, the following techniques have been proposed in the SCM model: an analysis technique for detecting infeasible paths (IFPs) from the program, and an analysis technique for generating various kinds of slices in a unified framework. This paper proposes a technique for accurately computing program slices using the IFPs in the SCM model. Next, it proposes a technique for improving the accuracy of detecting semantic errors during merging of several modifications by using accurate program slices. In addition, new applications are proposed for the various slices.

关键词： Computational linguistics

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parallel Algorithms for Deblurring of MR Images 13

Parallel Algorithms for Deblurring of MR Images

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13th International Conference on Computers and Their Applications, CATA 1998

作者： Menon, Padmanabhan Chaudhary, Vipin Pipe, James G. Parallel and Distributed Computing Laboratory Wayne State University DetroitMI48202 United States Department of Radiology Wayne State University DetroitMI48202 United States

ISBN: (纸本)9781618395443

This paper presents a parallelized algorithm for the deblurring of images obtained from Magnetic Resonance Imaging. Images generated by MRI may suffer a loss of clarity due to inhomogeneities in the magnetic field. One of the techniques for removing this blurring artifact is the demodulation of the data for each pixel of the image using the value of the magnetic field near that point in space. This method consists of acquiring a local field map, finding the best fit to a linear map and using it to deblur the image distortions due to local frequency variations. This is a very computation intensive operation and presents appreciable gains through parallelization. This paper presents the implementation of this algorithm using two popular message-passing platforms, PVM and MPI and discusses the pros and cons of each. A message-passing paradigm was chosen for parallelization since the target architecture is a network of workstations. Performance figures are presented for various problem and network sizes and future improvements are discussed. © 13th International Conference on Computers and Their Applications 1998, CATA 1998. All rights reserved.

关键词： Algorithms Image Processing Magnetic Resonance Imaging Message Passing MPI PVM

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Strings: a high-performance distributed shared memory for symmetrical multiprocessor clusters 98

Strings: a high-performance distributed shared memory for sy...

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International Symposium on High Performance distributed computing

作者： S. Roy V. Chaudhary Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

ISBN: (纸本)9780818685798

Introduces Strings, a high-performance distributed shared memory system designed for clusters of symmetrical multiprocessors (SMPs). The distinguishing feature of this system is the use of a fully multithreaded runtime system, written using POSIX threads. Strings also allows multiple application threads to be run on each node in a cluster. Since most modern UNIX systems can multiplex these threads on kernel-level lightweight processes, applications written using Strings can use all the processors in a SMP machine. This paper describes some of the architectural details of the system and analyzes the performance improvements with two example programs and a few benchmark programs from the SPLASH-2 suite.

关键词： Programming profession Yarn Microprocessors Workstations Sun Concurrent computing Laboratories Fuels Oceans Drugs

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parallel algorithms for simultaneous scheduling, binding and floorplanning in high-level synthesis

Parallel algorithms for simultaneous scheduling, binding and...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

With small device features in submicron technologies, interconnection delays play a dominant part in cycle time. Hence, it is important to consider the impact of physical design during high level synthesis. In comparison to a traditional approach which separates high-level synthesis from physical design, an algorithm which is able to make these stages interact very closely, would result in solutions with lower latency and area. However, such an approach could result in increased runtimes. parallel processing is an attractive way of reducing the runtimes. In this paper, two parallel algorithms for simultaneous scheduling, binding and floorplanning algorithm are presented. A detailed hardware model is considered, taking into account multiplexor and register areas and delays. Experimental results are reported on an IBM SP-2 multicomputer, with close to linear speedups for a set of benchmark circuits.

关键词： parallel algorithms High level synthesis Runtime Integrated circuit interconnections Delay effects Algorithm design and analysis parallel processing Scheduling algorithm Hardware Registers

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COMPILE TIME PARTITIONING OF NESTED LOOP ITERATION SPACES WITH NON-UNIFORM DEPENDENCES*

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parallel Algorithms and Applications 1997年第1-3期12卷 113-141页

作者： Swamy Punyamurtul - AMD Austin TX-78741 swamy@***[a] Vipin Chaudhary[a] Jialin Ju[a] Sumit Roy[a] [a] Dept. of Electrical and Computer Engineering Parallel and Distributed Computing Laboratory Detroit 48202

In this paper we address the problem of partitioning nested loops with non-uniform (irregular) dependence vectors. parallelizing and partitioning of nested loops requires efficient inter-iteration dependence analysis. Although many methods exist for nested loop partitioning, most of these perform poorly when parallelizing nested loops with irregular dependences. Unlike the case of nested loops with uniform dependences these will have a complicated dependence pattern which forms a non-uniform dependence vector set. We apply the results of classical convex theory and principles of linear programming to iteration spaces and show the correspondence between minimum dependence distance computation and iteration space tiling. Cross-iteration dependences are analyzed by forming an Integer Dependence Convex Hull (IDCH). Every integer point in this IDCH corresponds to a dependence vector in the iteration space of the nested loops. A simple way to compute minimum dependence distances from the dependence distance vectors of the extreme points of the IDCH is presented. Using these minimum dependence distances the iteration space can be tiled. Iterations within a tile can be executed in parallel and the different tiles can then be executed with proper synchronization. We demonstrate that our technique gives much better speedup and extracts more parallelism than the existing techniques.

关键词： nested loops partitioning Integer Dependence Convex

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A new metric for processor allocation schemes in multiprocessor systems

A new metric for processor allocation schemes in multiproces...

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IEEE International Conference on Performance, computing and Communications (IPCCC)

作者： S. Roy V. Chaudhary Parallel and Distributed Computing Laboratory Wayne State University Detroit MI USA

Recently a number of scalable interconnection networks for connecting multiple processors have been proposed. Though these networks differ in their properties such as bisection bandwidth, node degree, network diameter, and average diameter, there is one common problem that must be addressed by their designers. It should be possible to subdivide the set of processors such that the subset forms a smaller version of the underlying topology. This task is termed as Processor Allocation in general and Subcube allocation for Hypercubes. Various techniques appear in literature, including tree collapsing, free-list based approaches and others. A common metric for evaluating a scheme is the extent to which it can recognize all the possible sub-graphs in a particular network. In this paper are show that recognizability alone is a poor yardstick for predicting the performance of a processor allocation scheme. We introduce the ideas of Search Space and Impact Sets and propose a new, more pragmatic metric to measure the efficiencies of an allocation scheme. We evaluate this metric for a simple buddy strategy and a hypothetical exhaustive scheme for two popular interconnection networks, the Star Graph and the k-ary-n-cube. We support our results by simulation experiments and conclude that a scheme with higher recognizability is unlikely to justify the associated increase in complexity and storage requirements.

关键词： Hypercubes Multiprocessor interconnection networks Multiprocessing systems Operating systems Intelligent networks distributed computing Laboratories Joining processes Bandwidth Topology

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An efficient local address generation for the block-cyclic distribution 3

An efficient local address generation for the block-cyclic d...

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3rd International Conference on Algorithms and Architectures for parallel Processing, ICA3PP 1997

作者： Kwon, Oh-Young Kim, Tae-Geun Han, Tack-Don Yang, Sung-Bong Kim, Shin-Dug Distributed Computing Lab. Systems Engineering Research Institute 1 Ueun-dong Yusong-gu Taejon305-333 Korea Republic of Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul120-749 Korea Republic of

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time ΔM table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a ΔM table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time ΔM table generation method is faster than other algorithms in ΔM table generation time and access time for 10,000 array elements. © 1997 IEEE.

关键词： Virtual addresses

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A comparison of parallel approaches for algebraic factorization in logic synthesis

A comparison of parallel approaches for algebraic factorizat...

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International Symposium on parallel Processing

作者： S. Roy P. Banerjee Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel & Distributed Computing Northwestern University Evanston IL USA

Algebraic factorization is an extremely important part of any logic synthesis system, but it is computationally expensive. Hence, it is important to look at parallel processing to speed up the procedure. This paper presents three different parallel algorithms for algebraic factorization. The first algorithm uses circuit replication and uses a divide-and-conquer strategy. A second algorithm uses totally independent factorization on different circuit partitions with no interactions among the partitions. A third algorithm represents a compromise between the two approaches. It uses a novel L-shaped partitioning strategy which provides some interaction among the rectangles obtained in various partitions. For a large circuit like ex1010, the last algorithm runs 11.5 times faster over the sequential kernel extraction algorithms of the SIS sequential circuit synthesis system on six processors with less than 0.2% degradation in quality of the results.

关键词： Logic functions Circuit synthesis Partitioning algorithms Network synthesis Contracts parallel processing Laser sintering Degradation Logic design Sequential circuits

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An L-shaped partitioning-based algebraic factorization algorithm

An L-shaped partitioning-based algebraic factorization algor...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S. Roy P. Banerjee Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

Algebraic factorization is an extremely important part of any logic synthesis system but it is computationally expensive. Hence it is important to speed it up. The paper presents an algorithm to speedup the factorization by partitioning the circuit and performing factorizations on the sub-circuits. The approach clusters the entries of the co-kernel cube matrix into dense blocks using a novel L-shaped partitioning and searches these blocks for kernels. The L-shaped approach runs up to five times faster than the kernel extraction routine in SIS.

关键词： Partitioning algorithms Kernel Circuit synthesis distributed computing Network synthesis Contracts Logic functions Concurrent computing Clustering algorithms Logic design

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