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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： S. Roy P. Banerjee Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

Algebraic factorization is an extremely important part of any logic synthesis system but it is computationally expensive. Hence it is important to speed it up. The paper presents an algorithm to speedup the factorization by partitioning the circuit and performing factorizations on the sub-circuits. The approach clusters the entries of the co-kernel cube matrix into dense blocks using a novel L-shaped partitioning and searches these blocks for kernels. The L-shaped approach runs up to five times faster than the kernel extraction routine in SIS.

关键词： Partitioning algorithms Kernel Circuit synthesis distributed computing Network synthesis Contracts Logic functions Concurrent computing Clustering algorithms Logic design

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An efficient local address generation for the block-cyclic distribution

An efficient local address generation for the block-cyclic d...

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IEEE International Conference on Algorithms and Architectures for parallel Processing (ICAP)

作者： Oh-Young Kwon Tae-Geun Kim Tack-Don Han Sung-Bong Yang Shin-Dug Kim Distributed Computing Laboratory Systems Engineering Research Institute Taejon South Korea Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.

关键词： Runtime Equations distributed computing Systems engineering and theory parallel processing Laboratories Computer science parallel languages Upper bound Automata

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parallel global routing algorithms for standard cells

Parallel global routing algorithms for standard cells

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International Symposium on parallel Processing

作者： Z. Xing J. Chandy P. Banerjee Computer and Systems Research Laboratory University of Illinois Urbana IL USA Cadence Design Systems Chelmsford MA USA Center for Parallel and Distributed Computing Northwestern University Evanston IL USA

In this paper, we propose three different parallel algorithms based on a state-of-the-art global router called TimberWolfSC. The parallel algorithms have been implemented by using the Message Passing Interface (MPI), and have been evaluated on a wide range of parallel platforms such as the Sun SparcCenter 1000 and the Intel Paragon. Our experimental results show good speedups and qualities from two of these parallel algorithms. We have been able to reduce runtimes of some circuits from half an hour to 5 minutes, obtained speedups of about 4.0 to 5.0 on 8 processors, with less than 2-3% degradation of quality of the solutions.

关键词： Routing parallel algorithms distributed computing Message passing Pins Wire Contracts Concurrent computing Laboratories Sun

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Unique sets oriented partitioning of nested loops with non-uniform dependences 25

Unique sets oriented partitioning of nested loops with non-u...

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25th International Conference on parallel Processing, ICPP 1996

作者： Ju, Jialin Chaudhary, V. Parallel and Distributed Computing Laboratory Wayne State University DetroitMI United States

ISBN: (纸本)081867623X

Although many methods exist for nested loop partitioning, most of them perform poorly when parallelizing loops with non-uniform dependences. This paper addresses the issue of parallelizing nested loops with non-uniform dependences. The approach is based on convex hull theory, which has adequate information to handle non-uniform dependences. We introduce the concept of Complete Dependence Convex Hull, unique head and tail sets and abstract the dependence information into these sets. These sets form the basis of the iteration space partitions. The properties of the unique head and tail sets are derived using convex hull theory. Depending on the relative placement of these unique sets, the partitioning problem is grouped into several cases. Several partitioning schemes are also suggested for implementing the technique. Preliminary implementation results of the scheme on the Cray J916 and comparison with other schemes show a dramatic improvement in performance. © 1996 IEEE.

关键词： Computational geometry

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Unique sets oriented partitioning of nested loops with non-uniform dependences

Unique sets oriented partitioning of nested loops with non-u...

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International Conference on parallel Processing (ICPP)

作者： Jialin Ju V. Chaudhary Parallel and Distributed Computing Laboratory Wayne State University Detroit MI USA

关键词： Tail parallel processing distributed computing Laboratories Sparse matrices Contracts Processor scheduling Indium tin oxide Tiles

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Design and evaluation of an environment APE for automatic parallelization of programs

Design and evaluation of an environment APE for automatic pa...

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International Symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： V. Chaudhary Chengzhong Xu S. Roy Jialin Ju V. Sinha Laiwu Luo Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University MI USA

In this paper, we present the design and evaluation of a compiler system, called APE, for automatic parallelization of scientific and engineering applications on distributed memory computers. APE is built on top of SUIF compiler. It extends SUIF with capabilities in parallelizing loops with non-uniform cross-iteration dependencies, and in handling loops that have indirect access patterns. We have evaluated the effectiveness of SUIF with several CFD test codes, and found that SUIF handles uniform loops over dense and regular data structures very well. For non-uniform loops, an innovative and efficient parallelization approach based on convex theory have been proposed and is being implemented. We have also presented a class of scalable algorithms for parallel distribution and redistribution of unstructured data structures during parallelizing irregular loops.

关键词： Program processors distributed computing Concurrent computing Computational fluid dynamics Data structures Quantum computing Programming profession parallel processing Design engineering Optimizing compilers

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parallel image processing in heterogeneous computing network systems

Parallel image processing in heterogeneous computing network...

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IEEE International Conference on Image Processing

作者： P. Chalermwat N. Alexandridis P. Piamsa-Nga M. O'Connell Parallel and Distributed Computing Laboratory George Washington University Washington D.C. DC USA

We present a uniform construct of parallel programming for a set of image processing tasks based on our distributed computing primitive (DCP) concept. Our target architecture is a heterogeneous computing network system consisting of various high performance workstations connected through a local area network. We show that DCP has advantages over non-primitive PVM-based parallel approaches in three aspects: ease-of-use, automation, and optimization.

关键词： Image processing Computer networks Concurrent computing parallel programming distributed computing Computer architecture High performance computing Workstations Local area networks Automation

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parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs

Parallel algorithms for force directed scheduling of flatten...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

In this paper we present some novel algorithms for scheduling hierarchical signal flow graphs in the domain of high-level synthesis. There are several key contributions of this paper. First, we develop a novel extension of the force directed scheduling problem which naturally handles loops and conditionals by coming up with a scheme of scheduling hierarchical signal flow graphs. Second, we develop three new parallel algorithms for the scheduling problem. Third, our parallel algorithms are portable across a wide range of parallel platforms. We report results on a set of high-level synthesis benchmarks on 8-processor SGI Challenge and a network of 4 SUN SPARCstation5 work stations. Finally, while some parallel algorithms for VLSI CAD reported by earlier researchers have reported a loss of qualities of results, our parallel algorithms produce exactly the same results as the sequential algorithms on which they are based.

关键词： parallel algorithms Flow graphs Processor scheduling Concurrent computing Scheduling algorithm Contracts Cost function Broadcasting

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A standard cell global routing algorithm with net selection for over-the-cell routing

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ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE 1995年第12期78卷 102-115页

作者： Koide, T Suzuki, T Wakabayashi, S Yoshida, N Member Faculty of Engineering Hiroshima University Higashi-Hiroshima Japan 724 Associate Member Shin'ichi:Wakabayashi received his B.E. degree in Electrical Engineering and his M.E. and Ph.D. degrees in Systems Engineering from Hiroshima University in 1979 1981 and 1984 respectively. He was a Researcher at Tokyo Research Laboratory IBM Japan Ltd. in 1984-1988. Since 1988 he has been an Associate Professor on the Faculty of Engineering Hiroshima University. His research interests include VLSI CAD combinatorial optimization parallel and distributed algorithms and theory of computing. Dr. Wakabayashi is a member of the Institute of Electrical and Electronics Engineers the Association for Computing Machinery the Institute of Electronics Information and Communication Engineers and the Information Processing Society of Japan. Members

In the detailed routing for VLSI standard cell layout design, the over-the-cell channel routing, which utilizes the over-the-cell legion as the routing region, has been proposed. In this design method, after determining the net assignment to each channel in the global routing step, the track assignment both in channel and on over-the-cell regions is performed by an over-the-cell channel router. However, conventional global routing algorithms do not assume over-the-cell channel routing but conventional channel routing, Therefore, the minimization of channel density does not always successfully lead to the minimization of the final channel height. This paper presents a new global Touting method for standard cell layouts to determine global routes for each net in both channel and over-the-cell regions simultaneously. The standard cell layout design system GLORIA based on the proposed algorithm is developed, and the experimental results compared with the conventional global routing method that performs the over-the-cell channel routing after global-routing with TimberWolf-SC4.2c are reported. Experimental results showed that the proposed routing algorithm can route about 18.4 percent fewer number of tracks than the conventional routing method, and the effectiveness of the proposed method is shown. The experimental results of applying the proposed method to the three-layer routing layout model also are presented.

关键词： standard cell layout design CAD global routing over-the-cell routing

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parallel AND distributed TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETIC-FIELD MODELING

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

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