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2010 International Conference on Field-Programmable Technology, FPT'10

作者： Wu, Guiming Dou, Yong Wang, Miao National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China Jiangnan Institute of Computing Technology Wuxi 214083 China

ISBN: (纸本)9781424489817

In this paper, we present an automatic synthesis framework to map loop nests to processor arrays with local memories on FPGAs. An affine transformation approach is firstly proposed to address space-time mapping problem. Then a data-driven architecture model is introduced to enable automatic generation of processor arrays by extracting this data-driven architecture model from transformed loop nests. Some techniques including memory allocation, communication generation and control generation are presented. Synthesizable RTL codes can be easily generated from the architecture model built by these techniques. A preliminary synthesis tool is implemented based on PLUTO, an automatic polyhedral source-to-source transformation and parallelization framework. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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High performance and memory efficient implementation of matrix multiplication on FPGAs

High performance and memory efficient implementation of matr...

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2010 International Conference on Field-Programmable Technology, FPT'10

ISBN: (纸本)9781424489817

We present a high performance and memory efficient hardware implementation of matrix multiplication for dense matrices of any size on the FPGA devices. By applying a series of transformations and optimizations on the original serial algorithm, we can obtain an I/O and memory optimized block algorithm for matrix multiplication on FPGAs. A linear array of processing elements (PEs) is proposed to implement this block algorithm. We show significant reduction in hardware resources consuming compared to the related work while increasing clock frequency. Moreover, the memory requirement can be reduced to O(S) from O(S 2), where S is the block size. Therefore, more PEs can be integrated into the same FPGA devices. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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KC-GenRe: A Knowledge-constrained Generative Re-ranking Method Based on Large Language Models for Knowledge Graph Completion 30

KC-GenRe: A Knowledge-constrained Generative Re-ranking Meth...

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Joint 30th International Conference on Computational Linguistics and 14th International Conference on Language Resources and Evaluation, LREC-COLING 2024

作者： Wang, Yilin Hu, Minghao Huang, Zhen Li, Dongsheng Yang, Dong Lu, Xicheng Defense Innovation Institute Academy of Military Sciences China Information Research Center of Military Science China National Key Laboratory of Parallel and Distributed Computing China

ISBN: (纸本)9782493814104

The goal of knowledge graph completion (KGC) is to predict missing facts among entities. Previous methods for KGC re-ranking are mostly built on non-generative language models to obtain the probability of each candidate. Recently, generative large language models (LLMs) have shown outstanding performance on several tasks such as information extraction and dialog systems. Leveraging them for KGC re-ranking is beneficial for leveraging the extensive pre-trained knowledge and powerful generative capabilities. However, it may encounter new problems when accomplishing the task, namely mismatch, misordering and omission. To this end, we introduce KC-GenRe, a knowledge-constrained generative re-ranking method based on LLMs for KGC. To overcome the mismatch issue, we formulate the KGC re-ranking task as a candidate identifier sorting generation problem implemented by generative LLMs. To tackle the misordering issue, we develop a knowledge-guided interactive training method that enhances the identification and ranking of candidates. To address the omission issue, we design a knowledge-augmented constrained inference method that enables contextual prompting and controlled generation, so as to obtain valid rankings. Experimental results show that KG-GenRe achieves state-of-the-art performance on four datasets, with gains of up to 6.7% and 7.7% in the MRR and Hits@1 metric compared to previous methods, and 9.0% and 11.1% compared to that without re-ranking. Extensive analysis demonstrates the effectiveness of components in KG-GenRe. © 2024 ELRA Language Resource Association: CC BY-NC 4.0.

关键词： Knowledge graph

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COMPILE TIME PARTITIONING OF NESTED LOOP ITERATION SPACES WITH NON-UNIFORM DEPENDENCES*

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parallel Algorithms and Applications 1997年第1-3期12卷 113-141页

作者： Swamy Punyamurtul - AMD Austin TX-78741 swamy@***[a] Vipin Chaudhary[a] Jialin Ju[a] Sumit Roy[a] [a] Dept. of Electrical and Computer Engineering Parallel and Distributed Computing Laboratory Detroit 48202

In this paper we address the problem of partitioning nested loops with non-uniform (irregular) dependence vectors. parallelizing and partitioning of nested loops requires efficient inter-iteration dependence analysis. Although many methods exist for nested loop partitioning, most of these perform poorly when parallelizing nested loops with irregular dependences. Unlike the case of nested loops with uniform dependences these will have a complicated dependence pattern which forms a non-uniform dependence vector set. We apply the results of classical convex theory and principles of linear programming to iteration spaces and show the correspondence between minimum dependence distance computation and iteration space tiling. Cross-iteration dependences are analyzed by forming an Integer Dependence Convex Hull (IDCH). Every integer point in this IDCH corresponds to a dependence vector in the iteration space of the nested loops. A simple way to compute minimum dependence distances from the dependence distance vectors of the extreme points of the IDCH is presented. Using these minimum dependence distances the iteration space can be tiled. Iterations within a tile can be executed in parallel and the different tiles can then be executed with proper synchronization. We demonstrate that our technique gives much better speedup and extracts more parallelism than the existing techniques.

关键词： nested loops partitioning Integer Dependence Convex

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Galaxyfly: A novel family of flexible-radix low-diameter topologies for large-scales interconnection networks 16

Galaxyfly: A novel family of flexible-radix low-diameter top...

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30th International Conference on Supercomputing, ICS 2016

作者： Lei, Fei Dong, Dezun Liao, Xiangke Su, Xing Li, Cunlu National Laboratory for Parallel and Distributed Processing Collaborative Innovation Center of High Performance Computing College of Computer National University of Defense Technology Changsha410073 China

ISBN: (纸本)9781450343619

Interconnection network plays an essential role in the architecture of large-scale high performance computing (HPC) systems. In the paper, we construct a novel family of lowdiameter topologies, Galaxyfly, using techniques of algebraic graphs over finite fields. Galaxyfly is guaranteed to retain a small constant diameter while achieving a flexible tradeoff between network scale and bisection bandwidth. Galaxyfly lowers the demands for high radix of network routers and is able to utilize routers with merely moderate radix to build exascale interconnection networks. We present effective congestion-aware routing algorithms for Galaxyfly by exploring its algebraic property. We conduct extensive simulations and analysis to evaluate the performance, cost and power consumption of Galaxyfly against state-of-the-art topologies. The results show that our design achieves better performance than most existing topologies under various routing algorithms and traffic patterns, and is cost-effective to deploy for exascale HPC systems. © 2016 ACM.

关键词： Topology

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Computation and communication efficient graph processing with distributed immutable view 14

Computation and communication efficient graph processing wit...

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23rd ACM Symposium on High-Performance parallel and distributed computing, HPDC 2014

作者： Chen, Rong Ding, Xin Wang, Peng Chen, Haibo Zang, Binyu Guan, Haibing Shanghai Key Laboratory of Scalable Computing and Systems Institute of Parallel and Distributed Systems Shanghai Jiao Tong University China Shanghai Key Laboratory of Scalable Computing and Systems Department of Computer Science Shanghai Jiao Tong University China

ISBN: (纸本)9781450327480

Cyclops is a new vertex-oriented graph-parallel framework for writing distributed graph analytics. Unlike existing distributed graph computation models, Cyclops retains simplicity and computation-efficiency by synchronously computing over a distributed immutable view, which grants a vertex with read-only access to all its neighboring vertices. The view is provided via readonly replication of vertices for edges spanning machines during a graph cut. Cyclops follows a centralized computation model by assigning a master vertex to update and propagate the value to its replicas unidirectionally in each iteration, which can significantly reduce messages and avoid contention on replicas. Being aware of the pervasively available multicore-based clusters, Cyclops is further extended with a hierarchical processing model, which aggregates messages and replicas in a single multicore machine and transparently decomposes each worker into multiple threads ondemand for different stages of computation. We have implemented Cyclops based on an open-source Pregel clone called Hama. Our evaluation using a set of graph algorithms on an in-house multicore cluster shows that Cyclops outperforms Hama from 2.06X to 8.69X and 5.95X to 23.04X using hash-based and Metis partition algorithms accordingly, due to the elimination of contention on messages and hierarchical optimization for the multicore-based clusters. Cyclops (written in Java) also has comparable performance with PowerGraph (written in C++) despite the language difference, due to the significantly lower number of messages and avoided contention. Copyright © 2014 ACM.

关键词： Iterative methods

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A framework for constructing peer-to-peer overlay networks in java 09

A framework for constructing peer-to-peer overlay networks i...

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7th International Conference on Principles and Practice of Programming in Java, PPPJ 2009

作者： Rui, Shen Ji, Wang Shengdong, Zhang Siqi, Shen Pei, Fan National Laboratory for Parallel and Distributed Processing Changsha 410073 China School of Computing University of Leeds Leeds LS2 9JT United Kingdom

ISBN: (纸本)9781605585987

Peer-to-peer emerges as a better way for building applications on the Internet that require high scalability and availability. Peer-to-peer systems are usually organized into structured overlay networks, which provide key-based routing capabilities to eliminate flooding in unstructured ones. Many overlay network protocols have been proposed to organize peers into various topologies with emphasis on different networking properties. However, applications are often stuck to a specific peer-to-peer overlay network implementation, because different overlay implementations usually provide very different interfaces and messaging mechanisms. In this paper, we present a framework for constructing peer-to-peer overlay networks in Java. First, networking is abstracted by the interfaces that use URIs to uniformly address peers on different underlying or overlay networks. Then, asynchronous and synchronous messaging support is built upon these interfaces. Finally, overlay networking interfaces are sketched to handle specific issues in overlay networks. We have constructed several overlay networks in this framework, and built peer-to-peer applications which are independent of overlay implementations. Copyright 2009 ACM.

关键词： Overlay networks

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Concurrent and consistent virtual machine introspection with hardware transactional memory

Concurrent and consistent virtual machine introspection with...

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20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014

作者： Liu, Yutao Xia, Yubin Guan, Haibing Zang, Binyu Chen, Haibo Shanghai Key Laboratory of Scalable Computing and Systems Institute of Parallel and Distributed Systems Shanghai Jiao Tong University China Shanghai Key Laboratory of Scalable Computing and Systems Department of Computer Science Shanghai Jiao Tong University China

ISBN: (纸本)9781479930975

Virtual machine introspection, which provides tamperresistant, high-fidelity 'out of the box' monitoring of virtual machines, has many prominent security applications including VM-based intrusion detection, malware analysis and memory forensic analysis. However, prior approaches are either intrusive in stopping the world to avoid race conditions between introspection tools and the guest VM, or providing no guarantee of getting a consistent state of the guest VM. Further, there is currently no effective means for timely examining the VM states in question. In this paper, we propose a novel approach, called TxIntro, which retrofits hardware transactional memory (HTM) for concurrent, timely and consistent introspection of guest VMs. Specifically, TxIntro leverages the strong atomicity of HTM to actively monitor updates to critical kernel data structures. Then TxIntro can mount introspection to timely detect malicious tampering. To avoid fetching inconsistent kernel states for introspection, TxIntro uses HTM to add related synchronization states into the read set of the monitoring core and thus can easily detect potential inflight concurrent kernel updates. We have implemented and evaluated TxIntro based on Xen VMM on a commodity Intel Haswell machine that provides restricted transactional memory (RTM) support. To demonstrate the effectiveness of TxIntro, we implemented a set of kernel rootkit detectors using TxIntro. Evaluation results show that TxIntro is effective in detecting these rootkits, and is efficient in adding negligible performance overhead. © 2014 IEEE.

关键词： Malware

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Exploiting contention and congestion aware switch allocation in network-on-chips 17

Exploiting contention and congestion aware switch allocation...

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50th ACM Turing Conference - China, ACM TUR-C 2017

作者： Li, Cunlu Dongy, Dezun Liao, Xiangke National Laboratory for Parallel and Distributed Processing Collaborative Innovation Center of High Performance Computing College of Computer National University of Defense Technology Changsha Hunan410073 China

ISBN: (纸本)9781450348737

Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting congestion and contention information to load balance the traffic. However, most prior works do not consider balancing the traffic load during switch allocation. Due to the lack of congestion information in switch allocation stage, switch allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of switch. In this paper, we propose to add the congestion and contention information into the switch allocation process and design an efficient on-chip switching strategy which utilizes the contention and congestion information to load balance the traffic and achieve efficient switch allocation. To further enhance the performance of our design, we carefully design our switch allocation strategy to balance the trade-off between traffic load balance and the matching efficiency in switch allocation. We evaluate our design under synthetic traffic and trace of parsec benchmarks. Our evaluations show this mechanism achieves optimal latency compared to best previous switch allocation strategies. © 2017 ACM.

关键词： Network-on-chip

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Bipartite-oriented distributed graph partitioning for big learning 14

Bipartite-oriented distributed graph partitioning for big le...

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5th ACM Asia-Pacific Workshop on Systems, APSYS 2014

作者： Chen, Rong Shi, Jiaxin Zang, Binyu Guan, Haibing Shanghai Key Laboratory of Scalable Computing and Systems Institute of Parallel and Distributed Systems Shanghai Jiao Tong University China Shanghai Key Laboratory of Scalable Computing and Systems Department of Computer Science Shanghai Jiao Tong University China

ISBN: (纸本)9781450330244

Many machine learning and data mining (MLDM) problems like recommendation, topic modeling and medical diagnosis can be modeled as computing on bipartite graphs. However, most distributed graph-parallel systems are oblivious to the unique characteristics in such graphs and existing online graph partitioning algorithms usually causes excessive replication of vertices as well as significant pressure on network communication. This article identifies the challenges and opportunities of partitioning bipartite graphs for distributed MLDM processing and proposes BiGraph, a set of bipartite-oriented graph partitioning algorithms. BiGraph leverages observations such as the skewed distribution of vertices, discriminated computation load and imbalanced data sizes between the two subsets of vertices to derive a set of optimal graph partition algorithms that result in minimal vertex replication and network communication. BiGraph has been implemented on PowerGraph and is shown to have a performance boost up to 17.75X (from 1.38X) for four typical MLDM algorithms, due to reducing up to 62% vertex replication, and up to 96% network traffic. © 2014 ACM.

关键词： Data mining

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