The user interface of the object-oriented knowledge-based system CAOBS/v1.2 is a visual query subsystem consisting of a flexible visual query language (VKQL), and a knowledge base browser/editor. With the visual langu...
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The user interface of the object-oriented knowledge-based system CAOBS/v1.2 is a visual query subsystem consisting of a flexible visual query language (VKQL), and a knowledge base browser/editor. With the visual language, the user can express query requirements by constructing query graphs. VKQL absorbs the key features of some existing visual query languages, and adds more advanced functions. The paper presents the design and implementation of VKQL and compares VKQL with other similar query languages.
If a program is not executed as expected, we say that a semantic error has occurred in the program. As is well known, semantic errors sometimes appear in a program because the modification intention was not correctly ...
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If a program is not executed as expected, we say that a semantic error has occurred in the program. As is well known, semantic errors sometimes appear in a program because the modification intention was not correctly reflected in the new configuration. In order to avoid as many semantic errors as possible, as well as to efficiently locate errors, the authors are developing a semantic configuration management (SCM) model that is capable of efficiently performing various analyses of programs in a unified framework. Previously, the following techniques have been proposed in the SCM model: an analysis technique for detecting infeasible paths (IFPs) from the program, and an analysis technique for generating various kinds of slices in a unified framework. This paper proposes a technique for accurately computing program slices using the IFPs in the SCM model. Next, it proposes a technique for improving the accuracy of detecting semantic errors during merging of several modifications by using accurate program slices. In addition, new applications are proposed for the various slices.
In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array ...
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In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.
Presents a new approach for parallel machine simulation based on the discrete-event system specification (DEVS) formalism. Our simulation approach is directed toward parallel machine simulation at the concurrent threa...
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Presents a new approach for parallel machine simulation based on the discrete-event system specification (DEVS) formalism. Our simulation approach is directed toward parallel machine simulation at the concurrent threads level, and it is applicable for analysing the influence of internal algorithm/application concurrency on the performance characteristics of parallel machines. It uses as its modeling environment an abstraction of the parallel program's concurrent threads. The description of the modeled parallel machine is based on template models of the threads. We consider a program environment for discrete-event simulation of parallel computers based on our simulation approach. We also present some performance/utilization results from the simulation of a parallel database machine class, performed with our simulation environment.
In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic di...
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In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic di...
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ISBN:
(纸本)0780342291
In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.
The variable structure approach to multiple model state estimation for hybrid systems is utilized for radar tracking of manoeuvering aircraft. An adaptive digraph switching interacting multiple model tracking filter i...
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The variable structure approach to multiple model state estimation for hybrid systems is utilized for radar tracking of manoeuvering aircraft. An adaptive digraph switching interacting multiple model tracking filter i...
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The variable structure approach to multiple model state estimation for hybrid systems is utilized for radar tracking of manoeuvering aircraft. An adaptive digraph switching interacting multiple model tracking filter is developed. By computer simulation it is shown that the implemented versions of the proposed variable structure tracking filter significantly outperform the corresponding fixed structure versions with respect to performance-to-computational load ratio.
In the detailed routing for VLSI standard cell layout design, the over-the-cell channel routing, which utilizes the over-the-cell legion as the routing region, has been proposed. In this design method, after determini...
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In the detailed routing for VLSI standard cell layout design, the over-the-cell channel routing, which utilizes the over-the-cell legion as the routing region, has been proposed. In this design method, after determining the net assignment to each channel in the global routing step, the track assignment both in channel and on over-the-cell regions is performed by an over-the-cell channel router. However, conventional global routing algorithms do not assume over-the-cell channel routing but conventional channel routing, Therefore, the minimization of channel density does not always successfully lead to the minimization of the final channel height. This paper presents a new global Touting method for standard cell layouts to determine global routes for each net in both channel and over-the-cell regions simultaneously. The standard cell layout design system GLORIA based on the proposed algorithm is developed, and the experimental results compared with the conventional global routing method that performs the over-the-cell channel routing after global-routing with TimberWolf-SC4.2c are reported. Experimental results showed that the proposed routing algorithm can route about 18.4 percent fewer number of tracks than the conventional routing method, and the effectiveness of the proposed method is shown. The experimental results of applying the proposed method to the three-layer routing layout model also are presented.
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