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International Symposium on Database Applications in Non-Traditional Environments, DANTE

作者： Ming Xu Yong-Jun Wang Yi-Jie Wang Kang Zhang Yanchun Zhang National Laboratory for parallel and Distributed Processing Changsha Hunan China Department of Computing Macquarie University Sydney Australia Department of Mathematics & Computing University of Southern Queensland Toowoomba Australia

The user interface of the object-oriented knowledge-based system CAOBS/v1.2 is a visual query subsystem consisting of a flexible visual query language (VKQL), and a knowledge base browser/editor. With the visual language, the user can express query requirements by constructing query graphs. VKQL absorbs the key features of some existing visual query languages, and adds more advanced functions. The paper presents the design and implementation of VKQL and compares VKQL with other similar query languages.

关键词： Database languages Knowledge based systems Computer aided software engineering

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Semantic configuration management model using a path dependence flow graph

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Systems and Computers in Japan 1999年第5期30卷 47-55页

作者： Naoi, Kuniaki Takahashi, Naohisa NTT Software Laboratories Musashino 180 Japan NTT Optical Netwk. Syst. Labs. Musashino 180 Japan Waseda University Global Computing Laboratory NTT Software Laboratories Technical University Berlin Germany Info. Processing Society of Japan Japan Soc. Software Sci. Technol. ACM IEEE Computer Society University of Electro-Communications Tokyo Institute of Technology NTT Elec. Commun. Laboratories Parallel Distributed Arch.'s Res. G. NTT Optical Netwk. Syst. Labs. Info. Processing Society of Japan ACM

If a program is not executed as expected, we say that a semantic error has occurred in the program. As is well known, semantic errors sometimes appear in a program because the modification intention was not correctly reflected in the new configuration. In order to avoid as many semantic errors as possible, as well as to efficiently locate errors, the authors are developing a semantic configuration management (SCM) model that is capable of efficiently performing various analyses of programs in a unified framework. Previously, the following techniques have been proposed in the SCM model: an analysis technique for detecting infeasible paths (IFPs) from the program, and an analysis technique for generating various kinds of slices in a unified framework. This paper proposes a technique for accurately computing program slices using the IFPs in the SCM model. Next, it proposes a technique for improving the accuracy of detecting semantic errors during merging of several modifications by using accurate program slices. In addition, new applications are proposed for the various slices.

关键词： Computational linguistics

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Design of array processors for 2-D Discrete Fourier Transform

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1997年第4期E80D卷 455-465页

作者： Peng, ST Sedukhin, I Sedukhin, S Department of Computer Software Distributed Parallel Processing Laboratory University of Aizu Aizu-Wakamatsu-shi. 965 -80 Japan RandD Group Hiwada Electronic Corporation (Pioneer Group) Fukushima-ken 969-13 Japan

In this paper the design of systolic array processors for computing 2-dimensional Discrete Fourier Transform (2-D DFT) is considered. We investigated three different computational schemes for designing systolic array processors using systematic approach. The systematic approach guarantees to find optimal systolic array processors from a large solution space in terms of the number of processing elements and I/O channels, the processing time, topology, pipeline period, etc. The optimal systolic array processors are scalable, modular and suitable for VLSI implementation. An application of the designed systolic array processors to the prime-factor DFT is also presented.

关键词： algorithm mapping 2-dimensional discrete Fourier transform parallelprocessing systolic array processors VLSI architectures

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Discrete-event simulation of parallel machines

Discrete-event simulation of parallel machines

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Aizu International Symposium on parallel Algorithms/Architecture Synthesis

作者： V. Lazarov R. Iliev Laboratory for Parallel and Distributed Processing Bulgarian Academy of Sciences Sofia Bulgaria

Presents a new approach for parallel machine simulation based on the discrete-event system specification (DEVS) formalism. Our simulation approach is directed toward parallel machine simulation at the concurrent threads level, and it is applicable for analysing the influence of internal algorithm/application concurrency on the performance characteristics of parallel machines. It uses as its modeling environment an abstraction of the parallel program's concurrent threads. The description of the modeled parallel machine is based on template models of the threads. We consider a program environment for discrete-event simulation of parallel computers based on our simulation approach. We also present some performance/utilization results from the simulation of a parallel database machine class, performed with our simulation environment.

关键词： Discrete event simulation parallel machines Yarn Computational modeling Analytical models Concurrent computing Discrete event systems Performance analysis Algorithm design and analysis Application software

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An efficient local address generation for the block-cyclic distribution 3

An efficient local address generation for the block-cyclic d...

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3rd International Conference on Algorithms and Architectures for parallel processing, ICA3PP 1997

作者： Kwon, Oh-Young Kim, Tae-Geun Han, Tack-Don Yang, Sung-Bong Kim, Shin-Dug Distributed Computing Lab. Systems Engineering Research Institute 1 Ueun-dong Yusong-gu Taejon305-333 Korea Republic of Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul120-749 Korea Republic of

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time ΔM table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a ΔM table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time ΔM table generation method is faster than other algorithms in ΔM table generation time and access time for 10,000 array elements. © 1997 IEEE.

关键词： Virtual addresses

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An efficient local address generation for the block-cyclic distribution

An efficient local address generation for the block-cyclic d...

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IEEE International Conference on Algorithms and Architectures for parallel processing (ICAP)

作者： Oh-Young Kwon Tae-Geun Kim Tack-Don Han Sung-Bong Yang Shin-Dug Kim Distributed Computing Laboratory Systems Engineering Research Institute Taejon South Korea Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.

关键词： Runtime Equations distributed computing Systems engineering and theory parallel processing Laboratories Computer science parallel languages Upper bound Automata

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Performance evaluation and comparison of variable structure multiple-model algorithms for tracking maneuvering radar targets

Performance evaluation and comparison of variable structure ...

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1996 26th European Microwave Conference, EuMC 1996

作者： Jilkov, V.P. Angelova, D.S. Laboratory for Parallel and Distributed Processing Bulgarian Academy of Sciences 'Acad G. Bonchev' St Bl. 25-A 1113 Sofia Bulgaria

The variable structure approach to multiple model state estimation for hybrid systems is utilized for radar tracking of manoeuvering aircraft. An adaptive digraph switching interacting multiple model tracking filter is developed. By computer simulation it is shown that the implemented versions of the proposed variable structure tracking filter significantly outperform the corresponding fixed structure versions with respect to performance-to- computational load ratio. © 1996 IEEE.

关键词： Hybrid systems

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Performance evaluation and comparison of variable structure multiple-model algorithms for tracking maneuvering radar targets

Performance evaluation and comparison of variable structure ...

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European Conference on Microwave

作者： V P Jilkov D S Angelova Laboratory for Parallel and Distributed Processing Bulgarian Academy of Sciences Sofia Bulgaria

关键词： Radar tracking Target tracking State estimation Stochastic systems Aircraft Adaptive filters Computer simulation Time varying systems Noise measurement Time measurement

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A standard cell global routing algorithm with net selection for over-the-cell routing

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ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE 1995年第12期78卷 102-115页

作者： Koide, T Suzuki, T Wakabayashi, S Yoshida, N Member Faculty of Engineering Hiroshima University Higashi-Hiroshima Japan 724 Associate Member Shin'ichi:Wakabayashi received his B.E. degree in Electrical Engineering and his M.E. and Ph.D. degrees in Systems Engineering from Hiroshima University in 1979 1981 and 1984 respectively. He was a Researcher at Tokyo Research Laboratory IBM Japan Ltd. in 1984-1988. Since 1988 he has been an Associate Professor on the Faculty of Engineering Hiroshima University. His research interests include VLSI CAD combinatorial optimization parallel and distributed algorithms and theory of computing. Dr. Wakabayashi is a member of the Institute of Electrical and Electronics Engineers the Association for Computing Machinery the Institute of Electronics Information and Communication Engineers and the Information Processing Society of Japan. Members

In the detailed routing for VLSI standard cell layout design, the over-the-cell channel routing, which utilizes the over-the-cell legion as the routing region, has been proposed. In this design method, after determining the net assignment to each channel in the global routing step, the track assignment both in channel and on over-the-cell regions is performed by an over-the-cell channel router. However, conventional global routing algorithms do not assume over-the-cell channel routing but conventional channel routing, Therefore, the minimization of channel density does not always successfully lead to the minimization of the final channel height. This paper presents a new global Touting method for standard cell layouts to determine global routes for each net in both channel and over-the-cell regions simultaneously. The standard cell layout design system GLORIA based on the proposed algorithm is developed, and the experimental results compared with the conventional global routing method that performs the over-the-cell channel routing after global-routing with TimberWolf-SC4.2c are reported. Experimental results showed that the proposed routing algorithm can route about 18.4 percent fewer number of tracks than the conventional routing method, and the effectiveness of the proposed method is shown. The experimental results of applying the proposed method to the three-layer routing layout model also are presented.

关键词： standard cell layout design CAD global routing over-the-cell routing

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Trends in Neurosciences 1993年第5期16卷 P177-178页

作者： Mitsuo Kawato Hiroaki Gomi ATR Human Information Processing Research Laboratories Kyoto 619-02 Japan Laboratory of Parallel Distributed Processing Research Institute for Electronic Science Hokkaido University Sapporo Hokkaido 060 Japan

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